Impact of dislocation pits on device performances and interface quality degradation for E-mode recessed-gate Al2O3/GaN MOSFETs

Impact of dislocation pits on device performances and interface quality degradation for E-mode recessed-gate Al2O3/GaN MOSFETs
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位错坑对 E 模式凹栅 Al2O3/GaN MOSFET 器件性能和界面质量退化的影响

DOI:
10.1016/j.jallcom.2020.157144
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发表时间:
2021-02
影响因子:
6.2
通讯作者:
Yang Liu
Yang Liu
中科院分区:
材料科学2区
文献类型:
--
作者:
Liang He;Liuan Li;Taotao Que;Jinwei Zhang;Chenliang Feng;Zhenxing Liu;Qianshu Wu;Jia Chen;Qiuling Qiu;Yapeng Wang;Chenglang Li;Qi Zhang;Yang Liu

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直接观察和研究了Si衬底上e模Al_2O_3/GaNMOSFET中凹栅GaN表面位错坑对器件电学性能和MOS界面质量的影响。这些坑导致阈值电压(Vth)负移、大的栅漏电流和沟道导电恶化。此外,在Vth不稳定性中反映的严重的栅极俘获效应被证实与这些凹坑相关。这主要是由于形成了质量较差的MOS界面,界面陷阱密度大于1013 cm − 2 eV −1。进一步的实验测量表明,凹坑倾向于在凹陷的GaN表面上诱导有害的Ga-O,通常被称为界面陷阱的共同来源,从而导致不期望的效果。较低的凹坑密度有助于抑制Ga-O,并改善e模式MOS栅GaN晶体管的界面稳定性和器件性能。
The degradation of device electrical characterizations and MOS interfacial quality caused by dislocation pits on recessed-gate GaN surface are directly observed and investigated for e-mode Al2O3/GaN MOSFETs on Si substrate. The pits have resulted in negative shift of threshold voltage (Vth), large gate leakage current and deteriorated channel conduction. Moreover, the serious gate trapping effects reflected in Vthinstability are confirmed to be correlated with these pits. It has been mainly attributed to the formation of poor-quality MOS interface with high density of interface traps more than 1013cm−2eV−1. Further experimental measurements reveal that the pits tend to induce detrimental Ga–O on the recessed GaN surface, generally known as a common origin of interface traps, and thus cause the undesirable effects. A lower pits density helps to suppress the Ga–O, and improve the interface stability and device performances of e-mode MOS-gate GaN transistors.
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