Activity-Dependent Downscaling of Subthreshold Synaptic Inputs during Slow-Wave-Sleep-like Activity In Vivo.
Activity-Dependent Downscaling of Subthreshold Synaptic Inputs during Slow-Wave-Sleep-like Activity In Vivo.
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DOI:
10.1016/j.neuron.2018.01.047
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发表时间:
2018-03-21
期刊:
影响因子:
16.2
通讯作者:
Paulsen O
中科院分区:
文献类型:
--
作者:
González-Rueda A;Pedrosa V;Feord RC;Clopath C;Paulsen O
Activity-dependent synaptic plasticity is critical for cortical circuit refinement. The synaptic homeostasis hypothesis suggests that synaptic connections are strengthened during wake and downscaled during sleep; however, it is not obvious how the same plasticity rules could explain both outcomes. Using whole-cell recordings and optogenetic stimulation of presynaptic input in urethane-anesthetized mice, which exhibit slow-wave-sleep (SWS)-like activity, we show that synaptic plasticity rules are gated by cortical dynamics in vivo. While Down states support conventional spike timing-dependent plasticity, Up states are biased toward depression such that presynaptic stimulation alone leads to synaptic depression, while connections contributing to postsynaptic spiking are protected against this synaptic weakening. We find that this novel activity-dependent and input-specific downscaling mechanism has two important computational advantages: (1) improved signal-to-noise ratio, and (2) preservation of previously stored information. Thus, these synaptic plasticity rules provide an attractive mechanism for SWS-related synaptic downscaling and circuit refinement. Conventional STDP is seen only during Down states in vivo During Up states synaptic activation of L4 inputs leads to synaptic depression Postsynaptic spikes protect against Up state-mediated synaptic weakening These new plasticity rules improve S/N ratio and preserve stored information González-Rueda et al. show that presynaptic activation during slow-wave-sleep-like activity in vivo causes synaptic depression, unless it contributes to postsynaptic spiking. This plasticity rule offers an attractive mechanism for circuit refinement that improves signal-to-noise ratio and preserves previously stored information.
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