A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ
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使用互补开关电流源和时间松弛交错 DRRZ 的 14 位 500 MS/s CMOS DAC

DOI:
10.1109/tcsi.2014.2332248
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发表时间:
2014-07
期刊:
IEEE Transactions on Circuits and System I
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通讯作者:
魏琦
魏琦
中科院分区:
其他
文献类型:
--
作者:
魏琦

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采用0.13 μ mCMOS工艺设计并制作了一个14位500 MS/s电流舵型数模转换器(DAC)。对于传统的宽带电流舵DAC,无杂散动态范围(SFDR)受到码相关负载变化和码相关开关毛刺的非线性失真的限制。本文对它们进行了分析,并分别提出了互补开关电流源(CSCS)和时间松弛交错数字随机归零(TRI-DRRZ)。所提出的技术制造和测量,与SFDR的84.8 dB在11 MHz的信号频率和73.5 dB在244 MHz。该DAC采用1.2 V和2.5 V混合电源供电,功耗为299 mW,有效面积为1.85×0.65 mm 2。
A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 μm CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85×0.65 mm2.
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