A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ
A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ
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使用互补开关电流源和时间松弛交错 DRRZ 的 14 位 500 MS/s CMOS DAC
DOI:
10.1109/tcsi.2014.2332248
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发表时间:
2014-07
期刊:
影响因子:
--
通讯作者:
魏琦
中科院分区:
文献类型:
--
作者:
魏琦
A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 μm CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85×0.65 mm2.
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DOI:
10.1007/978-1-4614-1250-2
发表时间:
2013-02
期刊:
--
影响因子:
--
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期刊:
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2005-08
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影响因子:
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