A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology
复制标题
采用 65 nm CMOS 技术、具有 40 dB 均衡能力的 70 mW 25 Gb/s 四分之一速率 SerDes 发送器和接收器芯片组
DOI：
10.1109/tcsi.2016.2555250
复制
发表时间：
2016-06
影响因子：
5.1
通讯作者：
Wang Zhihua
中科院分区：
文献类型：
--
作者：
Yuan Shuai;Wu Liji;Wang Ziqiang;Zheng Xuqiang;Zhang Chun;Wang Zhihua
介绍了一种采用65 nm CMOS工艺设计的25 Gb/s收发芯片组。所提出的四分之一速率TX架构与分频器的时钟产生，不仅可以保证最高速度的串行化的时序约束，但也节省了传统的设计相比，功耗。源串联端接（SST）驱动器与2抽头前馈均衡器（FFE）和远端串扰消除器（XTC）是在TX芯片实现。RX芯片采用自适应四分之一速率2抽头判决反馈均衡器（DFE）和波特率时钟和数据恢复（CDR）。功率有效的DFE使用软判决技术和一个新的动态结构的组合。DFE自适应逻辑和波特率CDR逻辑共享一组误差采样器，以节省功耗和面积。提出了一种混合交替时钟方案，以满足时序要求，并进一步降低功耗。测量结果表明，TX和RX芯片组完全补偿了超过40 dB的奈奎斯特信道损耗，在25 Gb/s速率下工作时，1.2 V电源下功耗仅为70 mW。
A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feed-forward equalizer (FFE) and a far-end crosstalk canceller (XTC) is implemented in the TX chip. The RX chip employs an adaptive quarter-rate 2-tap decision-feedback equalizer (DFE) and a baud-rate clock and data recovery (CDR). The power-efficient DFE uses the combination of the soft-decision technique and a new dynamic structure. The DFE adaption logic and baud-rate CDR logic share a set of error samplers to save power and area. A hybrid alternate clock scheme is proposed to satisfy the timing requirement and reduce the power consumption further. The measurement results show that the TX and RX chipset totally compensates for a Nyquist channel loss of more than 40 dB, and consumes only 70 mW from a 1.2 V supply when operating at 25 Gb/s.
登录
查看更多内容
DOI：
10.1109/cicc.2010.5617597
发表时间：
2010-11
期刊：
IEEE Custom Integrated Circuits Conference 2010
影响因子：
--
作者：
Hae-Kang Jung;Soo-Min Lee;J. Sim;Hong-June Park
通讯作者：
Hae-Kang Jung;Soo-Min Lee;J. Sim;Hong-June Park
影响因子：
5.4
作者：
Shih-Yuan Kao;Shen-Iuan Liu
通讯作者：
Shih-Yuan Kao;Shen-Iuan Liu
影响因子：
5.4
作者：
P. Francese;T. Toifl;P. Buchmann;M. Braendli;C. Menolfi;M. Kossel;T. Morf;L. Kull;T. Andersen
通讯作者：
P. Francese;T. Toifl;P. Buchmann;M. Braendli;C. Menolfi;M. Kossel;T. Morf;L. Kull;T. Andersen
影响因子：
5.4
作者：
Huaide Wang;Jri Lee
通讯作者：
Huaide Wang;Jri Lee
DOI：
10.1109/jssc.2014.2349974
发表时间：
2014-09
期刊：
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
影响因子：
--
作者：
H. Kimura;P. Aziz;Tai Jing;A. Sinha;R. Narayan;Hairong Gao;Ping Jing;Gary Hom;Anshi Liang;E. Zhang;A. Kadkol;R. Kothari;G. Chan;Yehui Sun;Benjamin Ge;Jason Zeng;K. Ling;Michael C. Wang;A. Malipatil;S. Kotagiri;Lijun Li;C. Abel;Freeman Y. Zhong
通讯作者：
H. Kimura;P. Aziz;Tai Jing;A. Sinha;R. Narayan;Hairong Gao;Ping Jing;Gary Hom;Anshi Liang;E. Zhang;A. Kadkol;R. Kothari;G. Chan;Yehui Sun;Benjamin Ge;Jason Zeng;K. Ling;Michael C. Wang;A. Malipatil;S. Kotagiri;Lijun Li;C. Abel;Freeman Y. Zhong