SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain

SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain
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用于保护制造供应链中的 IP 的 SAT-Hard 循环逻辑混淆

DOI:
10.1109/tvlsi.2020.2968552
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发表时间:
2020
期刊:
IEEE Transactions on Very Large Scale Integration (VLSI
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通讯作者:
Sasan, Avesta
Sasan, Avesta
中科院分区:
--
文献类型:
--
作者:
Roshanisefat, Shervin;Mardani Kamali, Hadi;Homayoun, Houman;Sasan, Avesta

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最先进的针对循环逻辑混淆的攻击使用了配备了一组循环避免子句的可满足性求解器。这些循环避免子句是在预处理步骤中生成的,并定义了各种键组合,可以在不使电路振荡或有状态的情况下打开或关闭循环。在本文中,我们证明了该预处理步骤必须在网络列表的所有循环上生成循环避免条件;否则,缺失的循环可能会使求解器陷入无限循环,或者使其以错误的密钥退出。然后,我们提出了几种技术,通过这些技术,循环数作为插入反馈数的函数呈指数增长。我们进一步说明,当反馈数量增加时,攻击预处理步骤的复杂性和运行时间呈指数增长,从而无法在合理的时间内正确组成循环回避子句。另一方面,如果没有完成预处理,则由可满足解算器制定的攻击将卡住或以错误的密钥退出。因此,当本文提出的条件下的循环混淆实现时,将给基于可满足解算器的攻击带来指数级难题。
State-of-the-art attacks against cyclic logic obfuscation use satisfiability solvers that are equipped with a set of cycle-avoidance clauses. These cycle-avoidance clauses are generated in a preprocessing step and define various key combinations that could open or close cycles without making the circuit oscillating or stateful. In this article, we show that this preprocessing step has to generate cycle-avoidance conditions on all cycles in a netlist; otherwise, a missing cycle could trap the solver in an infinite loop or make it exit with an incorrect key. Then, we propose several techniques by which the number of cycles is exponentially increased as a function of the number of inserted feedback. We further illustrate that when the number of feedback is increased, the preprocessing step of the attack faces an exponential increase in complexity and runtime, preventing the correct composition of cycle-avoidance clauses in a reasonable time. On the other hand, if the preprocessing is not concluded, the attack formulated by the satisfiability solver will either get stuck or exit with an incorrect key. Hence, when the cyclic obfuscation under the conditions proposed in this article is implemented, it would impose an exponentially difficult problem for the satisfiability solver-based attacks.
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