Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
复制标题
逻辑/时钟路径感知的高速扫描测试生成,以避免错误捕获失败并减少时钟拉伸
DOI:
10.1109/ats.2015.25
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发表时间:
2015
期刊:
影响因子:
--
通讯作者:
J. Qian
中科院分区:
文献类型:
--
作者:
K. Asada;X. Wen;S. Holst;K. Miyase;S. Kajihara;M. A. Kochte;E. Schneider;H.-J. Wunderlich;J. Qian
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.
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DOI:
10.1109/date.2008.4484642
发表时间:
2008-03
期刊:
--
影响因子:
--
作者:
D. Gizopoulos;K. Roy;P. Girard;N. Nicolici;X. Wen
通讯作者:
D. Gizopoulos;K. Roy;P. Girard;N. Nicolici;X. Wen
DOI:
10.1109/test.2003.1271091
发表时间:
2003
期刊:
International Test Conference, 2003. Proceedings. ITC 2003.
影响因子:
--
作者:
B. Benware;C. Schuermyer;S. Ranganathan;R. Madge;P. Krishnamurthy;Nagesh Tamarapalli;Kun;J. Rajski
通讯作者:
J. Rajski
DOI:
--
发表时间:
2005
期刊:
IEEE International Conference on Test, 2005.
影响因子:
--
作者:
J. Rearick;R. Rodgers
通讯作者:
R. Rodgers
影响因子:
2
作者:
T. McLaurin
通讯作者:
T. McLaurin