Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
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逻辑/时钟路径感知的高速扫描测试生成,以避免错误捕获失败并减少时钟拉伸

DOI:
10.1109/ats.2015.25
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发表时间:
2015
期刊:
2015 IEEE 24th Asian Test Symposium (ATS)
影响因子:
--
通讯作者:
J. Qian
J. Qian
中科院分区:
--
文献类型:
--
作者:
K. Asada;X. Wen;S. Holst;K. Miyase;S. Kajihara;M. A. Kochte;E. Schneider;H.-J. Wunderlich;J. Qian

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在全速扫描测试期间,捕获模式下的启动开关活动 (LSA) 引起的 IR 压降不仅会增加逻辑路径 (LP) 上的延迟,还会增加时钟路径 (Cps) 上的延迟。 LP 上过多的额外延迟会因错误捕获失败而影响测试良率,而 CP 上过多的额外延迟会因测试时钟延长而影响测试质量。本文首次通过一种新颖的 LCPA(逻辑/时钟路径感知)高速扫描测试生成方案来减轻 LSA 对 LP 和 CP 的影响,该方案具有以下特点:(1)基于 LP 和 CP 周围的 LSA 数量评估错误捕获失败风险的新指标,(2)通过减少 LP 周围的 LSA 或屏蔽不确定的测试响应来避免错误捕获失败的程序,以及(3)通过减少CP 周围的 LSA。实验结果证明了 LCPA 方案在提高测试良率和测试质量方面的有效性。
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.
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