Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs
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Ratatoskr：用于在 3D NoC 中进行深入功耗、性能和面积分析与优化的开源框架
DOI：
10.1145/3472754
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发表时间：
2021
期刊：
影响因子：
--
通讯作者：
Thilo Pionteck
中科院分区：
文献类型：
--
作者：
Jan Moritz Joseph;Lennart Bamberg;Imad Hajjar;Behnam Razi Perjikolaei;Alberto García-Ortiz;Thilo Pionteck
我们介绍了Ratatoskr，这是一个开源框架，用于深入的功耗，性能和面积（PPA）分析，用于3D集成和异构系统芯片（SoC）的片上网络（NoCs）。它通过提供寄存器传输级（RTL）的片上网络硬件实现、周期精确级的片上网络模拟器和事务级的应用模型，覆盖了抽象的各个层次。通过这种全面的方法，Ratatoskr可以提供以下具体的PPA分析：链路的动态功率可以在比特级仿真的2.4%精度内测量，同时保持周期精确的仿真速度。路由器功耗由RTL至门级综合与周期精确仿真相结合确定。整个NoC的性能可以通过周期精确和RTL仿真来测量。性能（即，从RTL合成结果获得各个路由器和NoC区域的时间间隔（例如，时间间隔）。尽管有这些多方面的功能，Ratatoskroffers简单的两步用户交互：（1）一个单一的进入点允许设置设计参数。(2)PPA报告自动生成。对于输入和输出，可以选择不同的抽象级别用于高级快速网络分析或架构细节的低级改进。可合成的NoC-RTL模型显示了与传统标准路由器相比改进的总路由器功率和面积。作为其他NoC PPA测量工具中没有的前瞻性和独特功能，Ratatoskr支持异构3D集成，这是即将到来的SoC最有前途的集成范例之一。因此，Ratatoskr奠定了基础，设计他们的通信架构。该框架可通过以下网址公开获取：http：github.com/ratatoskr-project。
We introduceRatatoskr, an open-source framework for in-depth power, performance, and area (PPA) analysis in Networks-on-Chips (NoCs) for 3D-integrated and heterogeneous System-on-Chips (SoCs). It covers all layers of abstraction by providing an NoC hardware implementation on Register Transfer Level (RTL), an NoC simulator on cycle-accurate level and an application model on transaction level. By this comprehensive approach,Ratatoskrcan provide the following specific PPA analyses: Dynamic power of links can be measured within 2.4% accuracy of bit-level simulations while maintaining cycle-accurate simulation speed. Router power is determined from RTL-to-gate-level synthesis combined with cycle-accurate simulations. The performance of the whole NoC can be measured both via cycle-accurate and RTL simulations. The performance (i.e., timing) of individual routers and the NoC area are obtained from RTL synthesis results. Despite these manifold features,Ratatoskroffers easy two-step user interaction: (1) A single point-of-entry allows setting design parameters. (2) PPA reports are generated automatically. For both the input and the output, different levels of abstraction can be chosen for high-level rapid network analysis or low-level improvement of architectural details. The synthesizable NoC-RTL model shows improved total router power and area in comparison to a conventional standard router. As a forward-thinking and unique feature not found in other NoC PPA-measurement tools,Ratatoskrsupports heterogeneous 3D integration that is one of the most promising integration paradigms for upcoming SoCs. Thereby,Ratatoskrlays the groundwork to design their communication architectures. The framework is publicly available athttps://github.com/ratatoskr-project.
ParTejas：多核处理器的并行模拟器
DOI：
--
发表时间：
2014
期刊：
IEEE International Symposium on Performance Analysis of Systems and Software
影响因子：
--
作者：
Geetika Malhotra;Pooja Aggarwal;Abhishek Sagar;S. Sarangi
通讯作者：
S. Sarangi
焦平面传感器处理器芯片
影响因子：
4.5
作者：
Á. Zarándy
通讯作者：
Á. Zarándy
DOI：
10.1109/tvlsi.2017.2713601
发表时间：
2017-06
影响因子：
2.8
作者：
Lennart Bamberg;Alberto García-Ortiz
通讯作者：
Lennart Bamberg;Alberto García-Ortiz