A method for achieving sub-2nm across-wafer uniformity performance
A method for achieving sub-2nm across-wafer uniformity performance
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一种实现亚 2nm 跨晶圆均匀性性能的方法
DOI：
10.1117/12.2662423
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发表时间：
2023
期刊：
影响因子：
--
通讯作者：
Chopra, Meghali J.
中科院分区：
文献类型：
--
作者：
Ban, Yang;Medina, Leandro;Da Silva, Michael;Naranjo, Sebastian;Chopra, Meghali J.
缩短工艺开发时间和加快上市时间是微电子行业长期面临的挑战。允许在整个晶片上进行优化的蚀刻模型的开发将使制造商能够优化工艺设计流程并在单个晶片运行之前预测工艺缺陷。跨晶片均匀性优化的挑战包括跨晶片的各种各样的特征、在等离子体腔室内以多个尺度发生的蚀刻变化、特征计量和计算上昂贵的模型开发。除了这些挑战之外，还要权衡数据质量和时间/成本效益、不同工具提供的各种测量信息以及人工收集数据的稀疏性和不一致性。我们解决这些挑战的功能和晶圆级建模方法。首先，针对各种蚀刻条件（例如，压力、气体成分、流速、温度、功率和偏压）。第二，基于OCD和/或横截面SEM测量在晶片上的多个位置处校准特征级模型。最后，校准模型用于预测一组最佳工艺条件，以保持整个晶片的均匀性并满足配方目标。我们使用SandBox Studio™ AI为FinFET应用演示了该方法。具体来说，我们展示了快速和自动化的特征级模型的校准，使用实验测量的3D功能蚀刻在各种工艺条件下。这里还使用Weave®对单个案例进行了X-SEM数据的自动图像分割，以演示如何在开发环境中快速获取此类数据。然后，我们证明了降阶模型预测最佳配方条件，以提高整体配方性能的有效性。我们展示了如何使用这种混合计量计算方法，可以捕获89.2%的晶圆产量的工艺窗口。
Reducing process development time and speeding up time to market are perennial challenges in the microelectronics industry. The development of etch models that permit optimizations across the wafer would enable manufacturers to optimize process design flows and predict process defects before a single wafer is run. The challenges of across-wafer uniformity optimizations include the large variety of features across the wafer, etch variations that occur at multiple scales within the plasma chamber, feature metrology, and computationally expensive model development. Compounding these challenges are trade-offs between data quality and time/cost-effectiveness, the wide variety of measurement information provided by different tools, and the sparsity and inconsistency of human-collected data. We address these challenges with a feature and wafer level modeling approach. First, experiments are conducted for a variety of etch conditions (e.g., pressure, gas composition, flow rate, temperature, power, and bias). Second, a feature level model is calibrated at multiple sites across the wafer based on OCD and/or cross-sectional SEM measurements. Finally, the calibrated model is used to predict an optimal set of process conditions to preserve uniformity across the wafer and to meet recipe targets. We demonstrate the methodology using SandBox Studio™ AI for a FinFET application. Specifically, we show the rapid and automated calibration of feature level models using experimental measurements of the 3D feature etch at a variety of process conditions. Automated image segmentation of X-SEM data is also performed here for single case using Weave®to demonstrate how such data can be acquired quickly in a development environment. We then demonstrate the effectiveness of the reduced-order model to predict optimal recipe conditions to improve overall recipe performance. We show how, with this hybrid-metrology computational approach, a process window that yields 89.2% of the wafer can be captured.
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DOI：
10.1117/12.2614284
发表时间：
2022
期刊：
Advanced Etch Technology and Process Integration for Nanopatterning XI
影响因子：
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作者：
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DOI：
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发表时间：
2017
期刊：
Advanced Lithography
影响因子：
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发表时间：
2022
期刊：
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DOI：
10.1117/12.2583868
发表时间：
2021
期刊：
Advanced Etch Technology and Process Integration for Nanopatterning X
影响因子：
--
作者：
Ban, Yang;Kearney, Kara;Sundahl, Bryan;Medina, Leandro;Bonnecaze, Roger T.;Chopra, Meghali J.
通讯作者：
Chopra, Meghali J.
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DOI：
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发表时间：
2020
期刊：
Advanced Lithography
影响因子：
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作者：
Leandro Medina;Bryan E. Sundahl;Meghali Chopra;R. Bonnecaze
通讯作者：
R. Bonnecaze