High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector
High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector
复制标题
专用于 CEPC 顶点检测器的 512 × 1024 像素阵列的高数据速率读出逻辑设计
DOI：
10.1088/1748-0221/14/12/c12012
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发表时间：
2019-12
影响因子：
1.3
通讯作者：
J. Guimaraes da Costa
中科院分区：
文献类型：
--
作者：
魏晓敏;W. Wei;T. Wu;Y. Zhang;X. Li;L. Zhang;W. Lu;Z. Liang;J. Dong;L. Li;J. Wang;R. Zheng;R. Casanova;S. Grinstein;Y. Hu;J. Guimaraes da Costa
CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. The characteristics of the sensing diode and the readout architecture were studied using several chips with small-scaled pixel array for CEPC vertex detector. This paper will study the design of a high data-rate readout logic design of a 512 × 1024 pixel array. For the innermost layer of CEPC vertex detector, the hit pixel frequency is near 120 MHz, which is several times higher than the design requirements of ALPIDE for ALICE vertex detector. Based on the hit-driven readout scheme in the pixel array of ALPIDE and FEI3, we propose a new peripheral readout logic design. All the double columns of pixels are read out in parallel and a fast readout architecrue of 512 double columns is realized. Meanwhile, a real-time data compression and a trigger-mode operation are supported to reduce the data output. The simulation results indicate the pixel hit frequency in average of 120 MHz can be processed with readout time of 50 ns per pixel and of less than 500 ns per double column of pixels. The layout area is 25.68 × 1.13 mm2. The power density in trigger mode and in triggerless mode are estimated as 25 ∼ 30 mW/cm2 and 35 ∼ 45 mW/cm2 respectively.
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影响因子：
1.3
作者：
L. Chen;H. Zhu;X. Ai;M. Fu;R. Kiuchi;Y. Liu;Z. Liu;X. Lou;Y. Lu;Q. Ouyang;X. Shi;J. Tao;K. Wang;N. Wang;C. Yang;Y. Zhang;Y. Zhou
通讯作者：
L. Chen;H. Zhu;X. Ai;M. Fu;R. Kiuchi;Y. Liu;Z. Liu;X. Lou;Y. Lu;Q. Ouyang;X. Shi;J. Tao;K. Wang;N. Wang;C. Yang;Y. Zhang;Y. Zhou
DOI：
--
发表时间：
2016-01
期刊：
--
影响因子：
--
作者：
V. Hoorn;J. Willem
通讯作者：
V. Hoorn;J. Willem
DOI：
10.1016/j.nima.2016.05.016
发表时间：
2017-02
影响因子：
1.4
作者：
G. Rinella
通讯作者：
G. Rinella
DOI：
10.1109/icecs46596.2019.8965105
发表时间：
2019-11
期刊：
2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
影响因子：
--
作者：
Tianya Wu;W. Lu;Jianing Dong;Long Li;W. Jia;R. Zheng;P. Yang;Guangming Huang;S. Grinstein;R. Casanova;Wei Wei-Wei;Xiaomin Wei;Ying Zhang;Liang Zhang;Xiaoting Li;Zhijun Liang;J. F. D. Costa
通讯作者：
Tianya Wu;W. Lu;Jianing Dong;Long Li;W. Jia;R. Zheng;P. Yang;Guangming Huang;S. Grinstein;R. Casanova;Wei Wei-Wei;Xiaomin Wei;Ying Zhang;Liang Zhang;Xiaoting Li;Zhijun Liang;J. F. D. Costa
DOI：
10.1016/j.nima.2016.03.031
发表时间：
2016-09
影响因子：
1.4
作者：
Ying Zhang;H. Zhu;Liang Zhang;M. Fu
通讯作者：
Ying Zhang;H. Zhu;Liang Zhang;M. Fu