A High Throughput List Decoder Architecture for Polar Codes
A High Throughput List Decoder Architecture for Polar Codes
复制标题
用于Polar码的高吞吐量列表解码器架构
DOI：
10.1109/tvlsi.2015.2499777
复制
发表时间：
2015-10
影响因子：
2.8
通讯作者：
Yan Zhiyuan
中科院分区：
文献类型：
--
作者：
Lin Jun;Xiong Chenrong;Yan Zhiyuan
虽然长极性代码可以实现任意二进制输入离散无内存通道的能力，而通过低复杂性连续策略（SC）算法解码时，SC算法的误差性能对于fini的极性代码不优于
While long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless channels when decoded by a low complexity successive-cancellation (SC) algorithm, the error performance of the SC algorithm is inferior for polar codes with finite block lengths. The cyclic redundancy check (CRC)-aided SC list (SCL) decoding algorithm has better error performance than the SC algorithm. However, current CRC-aided SCL decoders still suffer from long decoding latency and limited throughput. In this paper, a reduced latency list decoding (RLLD) algorithm for polar codes is proposed. Our RLLD algorithm performs the list decoding on a binary tree, whose leaves correspond to the bits of a polar code. In existing SCL decoding algorithms, all the nodes in the tree are traversed, and all possibilities of the information bits are considered. Instead, our RLLD algorithm visits much fewer nodes in the tree and considers fewer possibilities of the information bits. When configured properly, our RLLD algorithm significantly reduces the decoding latency and, hence, improves throughput, while introducing little performance degradation. Based on our RLLD algorithm, we also propose a high throughput list decoder architecture, which is suitable for larger block lengths due to its scalable partial sum computation unit. Our decoder architecture has been implemented for different block lengths and list sizes using the TSMC 90-nm CMOS technology. The implementation results demonstrate that our decoders achieve significant latency reduction and area efficiency improvement compared with the other list polar decoders in the literature.
登录
查看更多内容
DOI：
10.1109/iscas.2014.6865102
发表时间：
2014-06
期刊：
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
影响因子：
--
作者：
Chuan Zhang;X. You;Jin Sha
通讯作者：
Chuan Zhang;X. You;Jin Sha
DOI：
10.1109/tcsi.2013.2283779
发表时间：
2014-04
期刊：
IEEE Transactions on Circuits and Systems I: Regular Papers
影响因子：
--
作者：
Bo Yuan;K. Parhi
通讯作者：
Bo Yuan;K. Parhi
DOI：
10.1109/sips.2014.6986062
发表时间：
2014-05
期刊：
2014 IEEE Workshop on Signal Processing Systems (SiPS)
影响因子：
--
作者：
Jun Lin;Chenrong Xiong;Zhiyuan Yan
通讯作者：
Jun Lin;Chenrong Xiong;Zhiyuan Yan
影响因子：
2.5
作者：
Arikan, Erdal
通讯作者：
Arikan, Erdal
影响因子：
5.4
作者：
Chenrong Xiong;Jun Lin;Zhiyuan Yan
通讯作者：
Chenrong Xiong;Jun Lin;Zhiyuan Yan