Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN
Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN
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用于 WPAN 的 128 点 FFT/IFFT 功率优化实现的伪并行数据路径结构
DOI：
10.1007/s00034-011-9308-7
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
Mathew J
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文献类型：
--
作者：
Mathew J
提出了一种适用于低功耗IEEE 802.15.3a WPAN的128-PtFFT/IFFT的伪并行数据路径优化实现方案，将128-PtFFT分解为8-PtFFT和16-PtFFT，再将16-PtFFT分解为4×4和2×8。结果表明，对于给定的算法，存在最佳并行度。分析表明，在面积适度增加的情况下，可以实现显著的功率降低。该结构在不到312.5 ns的时间内完成一次并行到并行(即所有输入数据并行可用，所有输出数据并行产生)的128点快速傅立叶变换计算，从而满足标准规范。从算法和实现的角度分析了这些体系结构的优缺点。描述了在块级具有不同数量的数据路径的每个体系结构的详细功率分析。我们发现，从功耗的角度来看，具有8条数据路径的体系结构是最优的。最优情况下的核心功耗为60.6兆瓦，仅为最新报道的0.18u工艺下128点FFT设计的一半不到。此外，还探索了一种针对寄存器的单事件翻转(SEU)容错方案。SEU容错方案不会影响性能，但功耗增加了约42%。除了低功耗，所提出的结构的优点还包括降低硬件复杂度、规则的数据流和简单的基于计数器的控制。
An optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4 and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each of the architectures with a different number of data paths at block level is described. We found that from power perspective the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures include reduced hardware complexity, regular data flow and simple counter based control.
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DOI：
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发表时间：
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期刊：
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影响因子：
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