Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving
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用于延长故障时间和节能的激活感知裕度分配
DOI：
10.1109/tvlsi.2018.2862154
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发表时间：
2018
影响因子：
2.8
通讯作者：
Hashimoto Masanori
中科院分区：
文献类型：
--
作者：
Masuda Yutaka;Onoye Takao;Hashimoto Masanori
本文提出一种平均故障时间（MTTF）感知设计方法，在满足目标芯片寿命的同时最小化功耗。所提出的设计方法的主要贡献是明确地引入MTTF作为设计约束，并通过激活感知松弛分配（ASA）优化设计。通常，为了节省功耗，非本质关键路径中包含的门被缩小或替换为高电压门，其中非本质关键路径是在缩小和替换之前原本具有大时序松弛的时序路径。另一方面，ASA给予非本质关键路径时间松弛，减少了延迟与本质关键路径非常接近的活动路径的数量，而本质关键路径的时间松弛无法通过重新合成和分级来增加。所提出的优化包括预ASA电路设计和ASA实现。先前的预asa设计准备了几个具有不同时间限制的候选设计，并在功率方面选择最有希望的候选设计。对于这种选择，分析每个候选器件，以估计ASA后可以达到目标MTTF的最小电源电压。然后，利用整数线性规划方法选择一组触发器进行ASA，使其最大限度地减少网关失效概率之和，并执行ASA。我们评估了带和不带ASA的电路的MTTF，并检查了在满足目标MTTF（例如10年）的情况下可以节省多少功率。评估结果表明，采用ASA的电路最高可节省49.6%的电量。
This paper proposes a mean time-to-failure (MTTF) aware design methodology for minimizing power dissipation while satisfying target chip lifetime. The key contributions of the proposed design methodology are to explicitly introduce MTTF as a design constraint and optimize the design with activation-aware slack assignment (ASA). Conventionally, the gates included in nonintrinsic critical paths are downscaled or replaced with high-Vth gates for power savings, where the nonintrinsic critical paths are timing paths which originally had large timing slacks before the downscaling and replacement. On the other hand, ASA gives timing slacks to nonintrinsic critical paths and reduces the number of active paths whose delays are very close to those of intrinsic critical paths whose timing slacks cannot be increased by resynthesis and sizing. The proposed optimization includes both pre-ASA circuit design and ASA implementation. The former pre-ASA design prepares several design candidates that laid out with different timing constraints and selects the most promising candidate regarding power. For this selection, every candidate is analyzed to estimate minimum supply voltage after ASA that can achieve the target MTTF. Then, the proposed methodology selects a set of flip-flops for ASA using integer linear programming, such that it reduces the sum of gatewise failure probability maximumly, and performs ASA. We evaluate MTTF of circuits with and without ASA and examine how much power saving can be obtained while satisfying the target MTTF, e.g., 10 years. Evaluation results show that the circuits with ASA achieve up to 49.6% power saving.
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