Power Gating Aware Task Scheduling in MPSoC
Power Gating Aware Task Scheduling in MPSoC
复制标题
MPSoC 中的电源门控任务调度
DOI:
10.1109/tvlsi.2010.2055907
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发表时间:
2011-10
影响因子:
2.8
通讯作者:
Wang, Yu
中科院分区:
文献类型:
--
作者:
Xu, Jiang;Xu, Yan;Yang, Huazhong;Liu, Weichen;Wang, Yu
Shrinking the feature size allows more and better functions on a single chip. However, it makes multiprocessor system-on-chip (MPSoC) more susceptible to various reliability threats. Power supply noise is a major reliability problem faced by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large power/ground (P/G) noise and can cause timing divergence and even functional errors in surrounding processing units. Previous work on resilient architectures mainly focused on power/thermal management and neglected the important side-effect: P/G noise induced by power gating. In this paper, for the first time, we formulate a task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC. Two efficient algorithms are proposed to reduce noise protection penalty and improve MPSoC performance. Our experiments show that both simulated annealing and heuristic algorithms can achieve on average 25% performance improvement together with up to 80% noise protection penalty saving compared with the conservative stop-go method for short tasks (shorter than 20 K clock cycles). For longer tasks up to 200 K clock cycles, the performance improvement of our methods will become relatively low. However, we can still achieve at least 35.2% noise protection penalty saving. Furthermore, a lightweight online adjustment strategy accompanying the offline scheduling method is proposed to adapt to runtime variations and improve reliability.
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DOI:
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发表时间:
2005-01
期刊:
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作者:
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发表时间:
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影响因子:
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