Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability

Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability
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双星:异构内存系统中协调可靠性以实现高性能和可扩展性

DOI:
10.1145/3352460.3358262
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发表时间:
2019
期刊:
IEEE/ACM International Symposium on Microarchitecture
影响因子:
--
通讯作者:
Zhao, Jishen
Zhao, Jishen
中科院分区:
--
文献类型:
--
作者:
Liu, Xiao;Roberts, David;Ausavarungnirun, Rachata;Mutlu, Onur;Zhao, Jishen

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随着存储容量的扩展,传统的高速缓存和存储器层次结构设计在以低存储和性能成本确保高可靠性方面面临着越来越困难的挑战。3D芯片堆叠式DRAM高速缓存和非易失性存储器(NVRAM)的最新发展带来了解决可靠性、性能和容量挑战的良好机遇,这是因为这些技术具有不同的可靠性特征。然而,简单地用NVRAM替换DRAM并不能解决存储系统的可靠性问题,因为传统的存储系统设计在高速缓存和主存储器之间保持分开的可靠性方案。我们在本文中的目标是随着存储容量的扩展而实现可靠和高性能的存储层次设计。为此,我们提出了二进制Star,它协调了3D堆叠DRAM末级缓存和NVRAM主存之间的可靠性方案和一致的缓存回写,以维护缓存和内存层次结构的可靠性。二进制星通过与NVRAM磨损平衡相协调,显著降低了一致缓存写回的性能和存储开销。因此,双星比最先进的具有纠错功能的存储系统更可靠,提供更好的性能。在一组内存密集型工作负载上,我们表明,与最先进的纠错方案相比,Binary Star及时(FIT)减少了92.9%的内存故障,同时保留了不提供纠错的传统DRAM设计的99%的性能。
As memory capacity scales, traditional cache and memory hierarchy designs are facing increasingly difficult challenges in ensuring high reliability with low storage and performance cost. Recent developments in 3D die-stacked DRAM caches and nonvolatile memories (NVRAMs) introduce promising opportunities in tackling the reliability, performance, and capacity challenges, due to the diverse reliability characteristics of the technologies. However, simply replacing DRAM with NVRAM does not solve the reliability issues of the memory system, as conventional memory system designs maintain separate reliability schemes across caches and main memory. Our goal in this paper is to enable a reliable and high-performance memory hierarchy design, as memory capacity scales. To this end, we propose Binary Star, which coordinates the reliability schemes and consistent cache writeback between 3D-stacked DRAM last-level cache and NVRAM main memory to maintain the reliability of the cache and the memory hierarchy. Binary Star significantly reduces the performance and storage overhead of consistent cache writeback by coordinating it with NVRAM wear leveling. As a result, Binary Star is much more reliable and offers better performance than state-of-the-art memory systems with error correction. On a set of memory-intensive workloads, we show that Binary Star reduces memory failures in time (FIT) by 92.9% compared to state-of-the-art error correction schemes, while retaining 99% of the performance of a conventional DRAM design that provides no error correction.
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