CWC: A Companion Write Cache for Energy-Aware Multi-Level Spin-Transfer Torque RAM Cache Design
CWC: A Companion Write Cache for Energy-Aware Multi-Level Spin-Transfer Torque RAM Cache Design
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CWC：用于能源感知多级自旋转移扭矩 RAM 高速缓存设计的配套写入高速缓存
DOI：
10.1142/s0218126615500796
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发表时间：
2015-05
期刊：
影响因子：
--
通讯作者：
Tianzhou Chen
中科院分区：
文献类型：
--
作者：
Tiefei Zhang;Jixiang Zhu;Jun Fu;Tianzhou Chen
由于泄漏功率大，密度低，传统的SARM由于能量问题而不适合实现大型片上缓存。新兴的非易失性存储技术，如相变存储器（PCM）和自旋转移扭矩存储器（STT-RAM），具有低泄漏功率和高密度的优点，是片上高速缓存的理想选择。特别是，STT-RAM具有比PCM更长的耐用性和更短的访问延迟。目前STT-RAM有两种类型：单级单元（SLC） STT-RAM和多级单元（MLC） STT-RAM。与SLC STT-RAM相比，MLC STT-RAM具有更高的密度和更低的泄漏功率，这使其成为未来片上缓存的更有希望的候选人。然而，与SLC STT-RAM相比，MLC STT-RAM以几乎两倍的写延迟和能量为代价提高了密度。这些缺点降低了系统性能，减少了能源效益。为了缓解这些问题，我们提出了一种新的缓存组织，同伴写缓存（CWC），它是一种小型的全关联SRAM缓存，以主从方式与主MLC STT-RAM缓存一起工作。CWC的关键功能是吸收来自MLC STT-RAM缓存的耗能写更新。实验结果表明，与基准相比，CWC可以大大降低写能量和动态能量，提高MLC STT-RAM缓存的性能和续航时间。
Due to its large leakage power and low density, the conventional SARM becomes less appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), have advantages of low leakage power and high density, which makes them good candidates for on-chip cache. In particular, STT-RAM has longer endurance and shorter access latency over PCM. There are two kinds of STT-RAM so far: single-level cell (SLC) STT-RAM and multi-level cell (MLC) STT-RAM. Compared to the SLC STT-RAM, the MLC STT-RAM has higher density and lower leakage power, which makes it a even more promising candidate for future on-chip cache. However, MLC STT-RAM improves density at the cost of almost doubled write latency and energy compared to the SLC STT-RAM. These drawbacks degrade the system performance and diminish the energy benefits. To alleviate these problems, we propose a novel cache organization, companion write cache (CWC), which is a small fully associative SRAM cache, working with the main MLC STT-RAM cache in a master-and-servant way. The key function of CWC is to absorb the energy-consuming write updates from the MLC STT-RAM cache. The experimental results are promising that CWC can greatly reduce the write energy and dynamic energy, improve the performance and endurance of MLC STT-RAM cache compared to a baseline.
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DOI：
10.1145/2155620.2155659
发表时间：
2011-12
期刊：
2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
影响因子：
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作者：
Zhenyu Sun;Xiuyuan Bi;Hai Helen Li;W. Wong;Zhong-Liang Ong;Xiaochun Zhu;Wenqing Wu
通讯作者：
Zhenyu Sun;Xiuyuan Bi;Hai Helen Li;W. Wong;Zhong-Liang Ong;Xiaochun Zhu;Wenqing Wu
DOI：
10.1145/2228360.2228521
发表时间：
2012-06
期刊：
DAC Design Automation Conference 2012
影响因子：
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作者：
Lei Jiang;Bo Zhao;Youtao Zhang;Jun Yang
通讯作者：
Lei Jiang;Bo Zhao;Youtao Zhang;Jun Yang
DOI：
10.1109/date.2010.5457221
发表时间：
2010-03
期刊：
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
影响因子：
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作者：
Yongsoo Joo;Dimin Niu;Xiangyu Dong;Guangyu Sun;N. Chang;Yuan Xie
通讯作者：
Yongsoo Joo;Dimin Niu;Xiangyu Dong;Guangyu Sun;N. Chang;Yuan Xie
DOI：
10.1109/islped.2011.5993610
发表时间：
2011-08
期刊：
IEEE/ACM International Symposium on Low Power Electronics and Design
影响因子：
--
作者：
Yiran Chen;W. Wong;Hai Helen Li;Cheng-Kok Koh
通讯作者：
Yiran Chen;W. Wong;Hai Helen Li;Cheng-Kok Koh
DOI：
10.1145/1555754.1555801
发表时间：
2009-06
期刊：
--
影响因子：
--
作者：
Brian Rogers;A. Krishna;Gordon B. Bell;K. V. Vu;Xiaowei Jiang;Yan Solihin
通讯作者：
Brian Rogers;A. Krishna;Gordon B. Bell;K. V. Vu;Xiaowei Jiang;Yan Solihin