A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory.
A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory.
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DOI：
10.3390/mi13071070
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发表时间：
2022-07-05
期刊：
影响因子：
3.4
通讯作者：
中科院分区：
文献类型：
--
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在本文中，我们提出并分析了一种新的中介层通道结构与垂直双通孔，以实现高速信令和高带宽存储器（HBM）的低功耗。提出了一种基于3D电磁（EM）仿真的内插器通道的自电容和互电容的分析模型，并进行了验证。我们深入分析了新型中介层通道的电学特性，考虑了各种设计参数，如垂直介层过孔的高度和间距以及垂直通道的差距。基于频率依赖的集总电路电阻、电感和电容，我们分析了所提出的中介层通道的通道特性。在阻抗，插入损耗和远端串扰方面，我们分析了与由微带线和带状线组成的传统结构相比，所提出的插入器通道改善了信号完整性特性。与传统的最差情况相比，这是带状线，所提出的插入器通道的眼宽，眼高和眼抖动分别提高了17.6%，29%和9.56%，在8 Gbps。与传统的内插器通道相比，所提出的内插器通道可以通过最小化片外通道的自电容来降低约28%的动态功耗。
In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel.
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