A Method of Gate-level Circuit Yield Calculation Based on PTM
A Method of Gate-level Circuit Yield Calculation Based on PTM
复制标题
一种基于PTM的门级电路良率计算方法
DOI:
10.1016/j.procs.2017.03.147
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发表时间:
2017-04
期刊:
影响因子:
--
通讯作者:
Yujiao Huang
中科院分区:
文献类型:
--
作者:
Jie Xiao;William Lee;Xuhua Yang;Haigen Hu;Yujiao Huang
Many yield models have mainly focused on the system-level circuit, which ignores the effect of circuit structure on yield. Combining the layout structure information of the gate-level circuit, this paper firstly analyzed the growth characteristics of defects over aging time, topological structure, defect density of generalized gates and yield loss mechanisms. Second, the calculation method of the defect removal rate in aging was given, and then probability models of the yield loss of generalized gates were proposed. With consideration of the topological structure information of circuits, combining the above-mentioned models, the yields of some benchmark circuits were calculated by the iterative PTM method. Finally, the proposed model is validated by comparing its predictions with the results obtained by Poisson distribution, negative binomial distribution, and exponential distribution models. In addition, the effects of process parameters, aging time, and fault-tolerance techniques on circuit yield are analyzed, and some significant conclusions are made.
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DOI:
--
发表时间:
2009
期刊:
--
影响因子:
--
作者:
Jiang Jian-hui
通讯作者:
Jiang Jian-hui
影响因子:
4.9
作者:
Jie Xiao;Jianhui Jiang;Jiarong Liang
通讯作者:
Jie Xiao;Jianhui Jiang;Jiarong Liang
DOI:
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发表时间:
1993-06
期刊:
IEEE Trans. Computers
影响因子:
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通讯作者:
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影响因子:
1.6
作者:
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通讯作者:
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DOI:
10.1016/j.microrel.2010.07.154
发表时间:
2011-02
期刊:
Microelectron. Reliab.
影响因子:
--
作者:
Jie Han;Hao Chen;E. Boykin;J. Fortes
通讯作者:
Jie Han;Hao Chen;E. Boykin;J. Fortes