2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking
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用于 NAND 闪存堆叠的 2 Gb/s 15 pJ/b/芯片 电感耦合可编程总线
DOI：
10.1109/jssc.2009.2034431
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发表时间：
2009
期刊：
影响因子：
--
通讯作者：
T. Kuroda
中科院分区：
文献类型：
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作者：
Mitsuko Saito;Y. Sugimori;Y. Kohama;Y. Yoshida;N. Miura;H. Ishikuro;T. Sakurai;T. Kuroda
开发了一种无线通信技术，该技术使控制器芯片能够使用中继传输以2Gb/s的数据速率与其下方的64个NAND闪存芯片的堆栈进行随机访问通信（图13.5.1）。该技术可以应用于固态驱动器（SSD）中的存储器访问。无线接口允许移除高电容ESD保护器件，从而将功耗降低2倍，并将I/O电路布局面积减少40倍。将焊线用于电源和无线接口用于数据访问，将64芯片堆叠中的焊线数量从超过1，500条减少到不到200条。键合线数量的减少使得可以将64个芯片集成在一个封装中，这通常需要八个单独的封装。该无线接口基于堆叠芯片上的电感器之间的电感耦合。电感器向上和向下发射磁场。这会产生有意和无意的通信链接，这使得它很难用于同质堆叠。我们的技术使数据传输向上和向下的存储器读取和写入测量BER 10-12。通过对各个芯片进行适当的状态编程来实现功耗降低。
A wireless communication technique, which enables a controller chip to communicate with random access with a stack underneath it of 64 NAND Flash memory chips at a data rate of 2Gb/s using relayed transmission is developed (Fig. 13.5.1). This technique can be applied to memory access in solid-state drives (SSD). The wireless interface allows the removal of a highly capacitive ESD protection device and results in a 2× reduction in power consumption, and a 40× reduction in I/O circuit-layout area. Using bonding wires for the power supply and wireless interface for data access reduces the number of bonding wires in the 64-chip stack from over 1,500 wires to less than 200 wires. This reduction in the number of bonding wires makes it possible to integrate 64 chips in one package, which conventionally requires eight separate packages. This wireless interface is based on inductive coupling between inductors on the stacked chips. The inductors emit magnetic field both upwards and downwards. This creates both intentional and unintentional communication link, which makes it difficult to be used in homogeneous stacking. Our technique enables data delivery upwards and downwards for memory read and write with measured BER ≪ 10–12. Power reduction is achieved by proper state programming of individual chips.
用于芯片间时钟和数据链路的 1Tb/s 3W 电感耦合收发器
DOI：
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发表时间：
2006
期刊：
Technical report of IEICE Vol.106, No.71
影响因子：
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作者：
村山芳隆;小澤哲也;堀越直;薮上信;石山和志;荒井賢一;N.Miura
通讯作者：
N.Miura
DOI：
10.1109/isscc.2004.1332634
发表时间：
2004-09
期刊：
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)
影响因子：
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作者：
D. Mizoguchi;Y.B. Yusof;N. Miura;T. Sakura;T. Kuroda
通讯作者：
D. Mizoguchi;Y.B. Yusof;N. Miura;T. Sakura;T. Kuroda
具有发射功率控制方案的 195Gb/s 1.2W 3D 堆叠感应片间无线超级连接
DOI：
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发表时间：
2005
期刊：
Technical report of IEICE Vol.105, No.96
影响因子：
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作者：
小澤哲也;横田周子;堀越直;藪上信;石山和志;荒井賢一;N.Miura
通讯作者：
N.Miura