Design and Analysis of Fault-Tolerant Programmable Logic Arrays

为了在更大的芯片密度下实现产量的显著提高，许多半导体制造商已经成功地在存储芯片设计中采用了冗余技术，例如64K dram， 256K dram等。近年来，可编程逻辑阵列（Programmable Logic Arrays, PLAs）由于其结构的规整性，在超大规模集成电路（VLSI）中越来越多地用于实现布尔逻辑功能。本研究正在研究一种具有冗余的PLA替代设计，该设计将利用部分缺陷芯片的可修复性，以提高芯片产量。该研究的目标是设计和修复容错PLA，并将此设计概念应用于任何其他阵列逻辑，例如可编程阵列逻辑（PAL）以及晶圆级集成（WSI）设计。PLA结构的使用，特别是在VLSI微处理器的控制部分，提高了设计生产率，缩短了设计时间，简化了芯片的物理设计，并便于工程变更的实施。半导体器件制造商不断努力提高芯片的复杂性，降低产品的速度-功耗，提高可靠性并生产有用且具有成本效益的器件。然而，增加芯片的复杂性会增加芯片出现缺陷的可能性，从而增加成本。提出的研究将提供新的设计和维修方案，以提高芯片的产量。

To attain significant improvements in yield with greater chip density, many semiconductor manufacturers have successfully employed redundancy techniques in the memory chip design, such as 64K DRAMs, 256K DRAMs, etc. Recently, due to the regular structure, Programmable Logic Arrays (PLAs) have become increasingly common for implementing Boolean logic functions in VLSI. This research is investigating an alternative PLA design with redundancy that will exploit the repairability of the partially defective chips in order to enhance the chip yield. The objectives of the research are to design and repair a fault-tolerant PLA and apply this design concept to any other array logic, such as programmable array logic (PAL), as well as Wafer-Scale Integration (WSI) design. The use of PLA structure, particularly in the control portion of a VLSI microprocessor, improves design productivity, shortens design time, simplifies the physical design of the chip, and facilitates the implementation of engineering changes. Semiconductor device manufacturers, continuously strive to increase chip complexity, reduce the speed-power product, increase reliability and produce useful and cost-effective devices. However, increasing the chip complexity would enhance the probability of having defective chips and then increase the cost. The proposed research will provide the new design and repair scheme to enhance the chip yields.