VLSI Implementation of Neural - Type Cells

本研究致力于神经型细胞超大规模集成电路芯片的理论设计、分析与实现。神经类型单元具有使其适合包含在神经网络中的许多属性；例如，由输入幅度控制的输出脉冲重复率。本文的研究内容是：首先，设计、研究和分析了神经型单元的方程，得到了允许最优磁滞尺寸的器件参数。其次，进行了电路的VLSI版图制作和仿真，以验证电路特性。计划包括基于该设计制造VLSI芯片，并将其集成到神经网络中进行性能测量。这项工作是与马里兰大学的神经网络研究一起完成的。

This research addresses the theoretical design, analysis and implementation of a VLSI chip for a neural-type cell. The neural-type cell has a number of properties that make it suitable for inclusion in a neural network; for example, an output pulse repetition rate controlled by input amplitude. The research is to: first, design, study and analyze the equations for the neural-type cell and obtain the device parameters which allow optimal size of hysteresis. Second, the VLSI layout for the circuit is being made and simulated to verify circuit characteristics. Plans include fabricating a VLSI chip based on the design, and integrating it into a neural network for performance measurement. This work is being done in conjunction with neural-net research at the University of Maryland.