ROW: Feasibility Study of a New Design Technique for Algorithm Specific VLSI Circuits

本研究的目的是：(A)开发一个预测超大规模集成(VLSI)算法速度的模型；(B)研究一种新的设计技术的可行性，该设计技术可以为一类时间关键型算术计算寻找全局的、时间优化的VLSI体系结构；(C)研究和制定明确的设计在吞吐量、延迟和芯片面积之间的权衡；(D)开发和自动化设计最优VLSI架构的新程序；以及(E)评估拟议设计技术的好处。

The objectives of this research are (a) to develop a model for predicting the speed of VLSI (very large scale integrated) algorithms; (b) to study the feasibility of a new design technique for finding global, time-optimized VLSI architectures for a class of time-critical arithmetic computations; (c) to investigate and formulate explicitly design tradeoffs among throughput, latency and chip area; (d) to develop and automate new procedures for designing optimal VLSI architectures; and (e) to evaluate the benefits of the proposed design technique.