RUI: A VLSI Arithmetic Data Path for a Complex Number Digital Signal Processor

本计画主要探讨复数运算之演算法与电路之设计与实作。 这项研究的动机是需要这些电路在高速数字信号处理应用。 研究的目标是： 1. 为复数数字信号处理器的算术数据路径开发VLSI设计算法。 2. 设计和实现超大规模集成电路和组件的开发算法，重点是架构和电路设计。 3. 研究芯片面积和VLSI电路延迟/吞吐量之间的权衡，并开发一个设计曲线，展示基准复数应用程序的权衡。 4. 指定复数数字信号处理器的其他数据路径元件，以支持高吞吐量输入/输出操作并易于编程。

This project deals with the design and implementation of VLSI algorithms and circuits for arithmetic operations on complex numbers. The research is motivated by the need for these circuits in high-speed digital signal processing applications. The goals of the research are to: 1. Develop VLSI design algorithms for the arithmetic data path of complex number digital signal processors. 2. Design and implement VLSI circuits and components for the developed algorithms, with emphasis on both architecture and circuit design. 3. Study the trade-off between chip area and VLSI circuit latency/throughput and to develop a design curve exhibiting their trade-offs for benchmark complex number applications. 4. Specify other data path components for the complex number digital signal processor to support high-throughput input/output operations and ease of programming.