RUI: A VLSI Arithmetic Data Path for a Complex Number Digital Signal Processor

本课题主要研究复数运算的VLSI算法和电路的设计与实现。研究的动机是高速数字信号处理应用中对这些电路的需求。研究的目标是：1.开发复数数字信号处理器算术数据通路的VLSI设计算法。2.针对所提出的算法，设计并实现了VLSI电路和元器件，重点从体系结构和电路设计两个方面进行了阐述。3.研究了芯片面积和VLSI电路延迟/吞吐量之间的权衡关系，并针对基准复数应用开发了一条显示它们权衡关系的设计曲线。4.指定复数数字信号处理器的其他数据路径组件，以支持高吞吐量输入/输出操作和易于编程。

This project deals with the design and implementation of VLSI algorithms and circuits for arithmetic operations on complex numbers. The research is motivated by the need for these circuits in high-speed digital signal processing applications. The goals of the research are to: 1. Develop VLSI design algorithms for the arithmetic data path of complex number digital signal processors. 2. Design and implement VLSI circuits and components for the developed algorithms, with emphasis on both architecture and circuit design. 3. Study the trade-off between chip area and VLSI circuit latency/throughput and to develop a design curve exhibiting their trade-offs for benchmark complex number applications. 4. Specify other data path components for the complex number digital signal processor to support high-throughput input/output operations and ease of programming.