RUI: VLSI Architectures and Circuits for Data Compression

许多应用程序的巨大数据需求与传输和存储系统有限的能力之间的差距决定了开发高性能数据压缩硬件的必要性。考虑到当前和不久的将来的技术，本研究的重点是研究和实现适合于VLSI实现的非平稳多字母源编码算法；面向实时应用的高吞吐量电路的实现；以及在芯片面积受限的情况下确定压缩性能和电路配置之间的最佳折衷。开发的算法和电路有望为通信和存储系统提供更具成本效益的数据压缩。

The gap between huge data requirements of many applications and limited capabilities of transmission and storage systems dictated the need for developing high-performance data compression hardware. This research focuses on the study and implementation of nonstationary multi-alphabet source coding algorithms suitable for VLSI implementations, given the current and near-future technology; the implementation of high-throughput circuits for real-time applications; and the determination of an optimal tradeoff between the compression performance and circuit configurations given constrained chip area. The developed algorithms and circuits are excepted to offer more cost-effective data compression for communication and storage systems.