Vector Processors for Systolic Arrays

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The digital signal and image processing industry continues to grow. However, many compute-bound, high-end, real-time needs are not currently being met. Application areas typifying these requirements are communications, radar/sonar, speech and scene analysis, computer vision and graphics. A new and powerful class of digital processor architectures is required to meet this need. This research is on a new digital processor design that has potential for significant increases in speed, area-speed and cost-performance measures. It can provide multi-megahertz fixed and floating point operation on one VLSI chip. Its innovative bit-serial interprocessor I/O structure makes it a candidate for fine-grain systolic array applications. The design goal is a system which achieves ten to one hundred MFLOP per chip computational bandwidth in a small, low cost package. This is in the class of desktop supercomputers. Such a machine could be used as an attached co-processor in general applications or embedded into signal and imaging systems in application specific environments. Reviewers gave this scores of 15, 15 and 18, which are quite high relative to all the scores. The three reviewers saw this as having al well-developed research plan, with high probability of good results leading to Phase II work. They said it is an important problem with substantial payoff. Solutions will contribute to the design of future instruments that depend on rapid processing of large arrays of numbers. The qualifications of the personnel are excellent.