Very Large-Scale Integration High Throughput Rate Architectures for Systolic Array Processors

本研究的主要目的是开发一种基于最小二乘QR分解算法的高通量VLSI脉动阵列处理芯片(或芯片组)的预加工工程模型。该芯片是为一般的脉动卡尔曼滤波应用而开发的。一个直接的应用是提高目前在商业全球定位系统(GPS)接收器中可以实现的跟踪精度和吞吐量。在第一阶段中，成功地论证了开发用于高通量信号处理器的脉动阵列LS结构的可行性。第二阶段的脉动阵列设计基于第一阶段提出的改进的快速Givens算法。第一阶段确定的新的基于算法的容错方法被进一步发展，包括基于QR脉动阵列固有的并行处理特性的故障识别和自动重构。预制芯片模型的开发需要确定以下用于脉动处理器的VLSI设计技术：算法到体系结构的依赖图映射、大尺寸问题到固定大小体系结构的划分；内部和I/O线路的权衡；以及数据流和计算的软件模拟。这项第二阶段的研究工作开发了可扩展到通用VLSI Systolal LS处理器的方法，从而使这项技术未来可以很容易地商业化到其他信号处理应用。

The major objective of this research effort is to develop a pre- fabrication engineering model of a high throughput VLSI systolic array processing chip (or chip set) based on least-square (LS) QR decomposition algorithm. This chip is being developed for general systolic Kalman filtering applications. An immediate application is to improve the tracing accuracies and throughput currently achievable in commercial Global Position Systems (GPS) receivers. In Phase I, the feasibility of developing systolic array LS architectures for high throughput rate signal processors has been successfully demonstrated. The systolic array design in Phase II is based on the modified Fast Givens algorithm developed in Phase I. The novel algorithm-based fault- tolerant approach identified in Phase I is further developed to include fault-identification and automatic reconfiguration based on inherent parallel processing characteristics of the QR systolic arrays. Development of the pre-fabrication chip model requires determination of the following VLSI design technologies for systolic processors: dependence graph mapping of algorithms to architecture, partitioning of large size problems to fixed size architecture; tradeoffs on internal and I/O lines; and software simulation of data flow and computations. This Phase II research effort develops methodologies which can be extended to general VLSI systolic LS processors and thus allow easy future commercialization of this technology to other signal processing applications.