Low-Cost Testing Techniques for VLSI Systems

时序逻辑电路和系统的测试是本研究的主题。 解决这一问题通常需要的成本，对许多人来说， 应用程序太强大，无法广泛采用。 目标是 找到降低时间、面积和测试开销的低成本技术 同时保持高故障覆盖率。 采取方法是 使用部分扫描和部分BIST的概念，这在 测试时序电路。 研究的一个重点是开发新的 测试性的措施和一个新的标准，扫描元件的选择。 第二是系统地避免现有技术的要素， 造成高成本。 正在开发有效的测试算法 通过使用从关于实际测试的信息导出的扫描元件 生成器. 用实验工具进行实质性的经验评价 使用真实的电路。

Testing sequential logic circuits and systems is the research subject. Solutions to this problem usually require costs that are, for many applications, too formidable to allow wide adoption. The goal is to find low cost techniques that reduce overhead of time, area and test data volume while maintaining high fault coverage. The approach is to use the notions of partial scan and partial BIST, which show promise in testing sequential circuits. One research thrust is to develop new measures of testability and a new criteria for scan element selection. A second is to systematically avoid elements of existing techniques that contribute to high costs. Effective test algorithms are being developed by using scan elements derived from information about the actual test generator. Substantial empirical evaluation with experimental tools using real circuits is being done.