Built-In Self-Test for Random Pattern Resistant Faults

本文研究的是具有抗随机模式故障的电路的测试技术。重点介绍了随机图样可测试电路的合成方法。正在开发的综合算法包括随机模式可测试的二级和多级组合逻辑的设计算法；对某些顺序逻辑类的扩展也在研究之中。研究了加权元胞自动机和固定位偏置伪随机模式发生器两种方法。

This research is on techniques for testing circuits having random pattern resistant faults. The focus is on methods for synthesizing random pattern testable circuits. The synthesis algorithms being developed include algorithms for design of random pattern testable two level and multi-level combinational logic; extensions to some classes of sequential logic are also being investigated. Two methods being pursued are weighted cellular automaton, and fixed bit biased pseudo-random pattern generator.