Towards Automatic Synthesis of Behavioral VHDL

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This is a Research Planning Grant for Women Scientists and Engineers. A research program in automating the synthesis of the VHDL language from a very high-level architectural specification is being planned. The approach is to transition state-of-the-art software synthesis technology to CAD design automation. A feasibility study of several high-level architectural specification models, which are implementation independent, is being conducted. Other activities are: defining a set of VHDL software synthesis operators, developing representations of pure behavioral level architectural specifications, and performing feasibility tests of these specifications.