General-Purpose Parallel Architectures

这项研究旨在为未来的大规模并行计算机建立一个首选的互连网络。这样的网络必须具有随着处理器数量的增加而适度增加的硬件要求，但也必须有效地支持一般通信模式。硬件成本等同于模型下的物理空间，该模型考虑了导线的最小宽度和间距规则。这与通常使用面积作为芯片成本衡量标准是一致的。将特别注意确保通用通信能力，即使在处理器间距离很大和出现故障时也是如此。这项工作将使用数学证明和模拟所提出的网络。选择首选的通用互连网络将允许开发更可移植和更持久的并行算法和程序。

This research seeks to establish a preferred interconnection network for massively parallel computers of the future. Such a network must have modestly increasing hardware requirements as the number of processors increases but also must efficiently support general patterns of communication. Hardware cost is equated with physical space under a model accounting for minimum width and spacing rules for wires. This is in keeping with the common use of area as a cost measure for chips. Particular attention will be given to ensuring that general-purpose communication capabilities hold up even when interprocessor distances are large and when faults are introduced. This work will employ both mathematical proof and simulation of proposed networks. The choice of a preferred general-purpose interconnection network will allow for the development of more portable and long-lasting parallel algorithms and programs.