Parallel-on-Demand --- A Broad Purpose 3D-Integrated Performance Acceleration Layer for General Purpose Processors

随着特征尺寸不断缩小的趋势和工艺技术的进步，在不久的将来，在芯片上集成100亿至1000亿个晶体管是可行的。然而，必须解决一个基本的物理限制，即功耗，以实现这种趋势。功率不再是一个理想的特性，而是使未来众核处理器系统实用化的实际设计约束。 另一方面，3D芯片堆叠等新兴工艺技术实现了新的集成维度，并为改善带宽、延迟和功耗提供了新的机会。 考虑到这样的设计约束和新的机会，当前以MIMD方式集成的对称、同构多核处理器从功率和面积效率的角度来看将不适合作为可扩展的解决方案，尽管它们减少了实现工作量。特别是，对于具有固有的高数据级并行性的应用，可以设计利用3D堆叠的新架构。 在这项研究中，一个新的众核架构，称为按需定制（POD），将调查利用最大的性能，为给定的芯片面积和能源预算。POD没有使用传统的专用ASIC加速器，而是集成了性能加速层（PAL），该层使用3D裸片堆叠作为单独的裸片层紧密耦合。PAL利用了从大规模并行处理器中学到的许多想法，但专注于现代多方面的挑战，例如功率和面积效率，片上线延迟问题，片上互连，与无序内核的集成，向后/向前兼容性，虚拟化资源映射和可扩展性。3D集成的性能加速层作为一个管理单元功能应用，也使整个系统灵活，降低了不同目标市场的非经常性工程成本。此外，将研究新的编程模型，以简化程序员和POD之间的交互，整体硬件复杂性及其随之而来的功耗影响。这种3D片上众核架构的成功将为实现高度可扩展的计算提供基础，并具有显著的能源效率，为以最少的资源进行Peta-FLOPS计算铺平道路。

With the continuing trend of shrinking feature size and advances in process technology, it would be feasible to integrate 10 to 100 billion transistors on a chip in near future. Nevertheless, one fundamental physical limit, power consumption, must be addressed to enable such trend. Power is no longer a desirable feature but an actual design constraint in making future many-core processor systems practical. On the other hand, emerging process technologies such as 3D die stacking enables a new dimension of integration and provides new opportunities for improving bandwidth, latency, and power. Given such design constraints and new opportunities, the current symmetric, homogeneous multi-core processors integrated in a MIMD manner will be inappropriate as a scalable solution from power- and area-efficiency standpoints despite their reduced implementation effort. In particular, for applications with inherently high data-level parallelism, it is possible to design new architectures that exploit the 3D stacking. In this research, a new many-core architecture, called Parallel-On-Demand (POD), will be investigated to exploit the maximum performance for a given die area and energy budget. Instead of using conventional, special-purpose ASIC accelerators, POD integrates a performance acceleration layer (PAL), which is tightly coupled as a separate die layer using 3D die stacking. PAL leverages many ideas learned from massively parallel processors but focuses on modern multi-faceted challenges such as power and area efficiency, on-chip wire delay issues, on-chip interconnects, integration with out-of-order cores, backward/forward compatibility, virtualized resource mapping, and extensibility. A 3D-integrated performance acceleration layer applied as a snap-on feature also makes the entire system flexible, reducing non-recurring engineering cost for different target markets. Moreover, new programming models will be investigated to simplify the interaction between programmers and POD, overall hardware complexity and its ensuing power implications. The success of such 3D on-die many-core architecture will provide a foundation to enable highly scalable computation with substantial energy efficiency, paving the road to Peta-FLOPS computing with minimal resources.