General-Purpose Parallel Architectures and Routing Schemes

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9321388 Greenberg This research seeks to determine good interconnection networks and routing schemes for massively parallel computers of the future. Such networks must have modestly increasing hardware requirements as the number of processors increases but also must efficiently support general patterns of communication. Hardware cost will be measured by using models that account for real-world constraints such as pin-out and wiring area rather than more naive component counting. Particular attention will be given to ensuring that general-purpose communication capabilities hold up even when interprocessor distances are large and when faults are introduced. This work will employ both mathematical proof and simulation of proposed networks. The identification of a superior interconnection network can increase the programmer's flexibility. On one hand, machine-independent programs should be fairly efficiently executable. On the other hand, programs that choose to exploit specifics of the interconnection network will be more portable and scalable given a robust interconnection scheme that can be retained as the number of processors grows. ***