Control and Layout Issues in Performance-Driven, High- Level Synthesis

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Pangrle This research is focused on two problems of high level synthesis, control and datapath synthesis, and how the tradeoffs between the two affect layout and performance of VLSI designs. First is finding control/datapath tradeoffs based on high-level transformations performed on the control/data flow graph. Second is incorporation of layout considerations into the generation of the datapath connectivity. A new data path generation scheme that aims at producing datapaths with better performance and layout characteristics is being developed. This research is being performed within the basic framework of the Keystone System which automatically synthesizes and simulates all of the datapath components, the control logic, and the routing.