Control and Layout Issues in Performance-Driven, High- Level Synthesis

本文主要研究高级综合中的两个问题：控制综合和数据路径综合，以及两者之间的权衡如何影响VLSI设计的版图和性能。首先是基于在控制/数据流图上执行的高级转换来寻找控制/数据路径的权衡。第二是将布局考虑纳入数据路径连通性的生成。正在开发一种新的数据路径生成方案，旨在生成具有更好的性能和布局特性的数据路径。这项研究是在Keystone系统的基本框架内进行的，该系统自动综合和模拟所有数据路径组件、控制逻辑和布线。

Pangrle This research is focused on two problems of high level synthesis, control and datapath synthesis, and how the tradeoffs between the two affect layout and performance of VLSI designs. First is finding control/datapath tradeoffs based on high-level transformations performed on the control/data flow graph. Second is incorporation of layout considerations into the generation of the datapath connectivity. A new data path generation scheme that aims at producing datapaths with better performance and layout characteristics is being developed. This research is being performed within the basic framework of the Keystone System which automatically synthesizes and simulates all of the datapath components, the control logic, and the routing.