Integrated Interconnections for ULSI Using Silicon Wafer Area Networks (SWANs)

本研究探讨了一种新颖的、可扩展的智能晶圆级通信网络（硅晶圆区域网络或SWAN）的功能行为和VLSI实现，该网络支持具有可预测网络遍历时间的细粒度通信。选择网络的“智能”，自适应地、动态地建立具有点对点直接互联功能的虚拟互联，使个体信息在网络中传递。该网络被假设为晶圆级功能，通过利用高密度的IC布线，允许交换机之间的高度并行数据链路。网络组织类似于收缩处理阵列，使用最近邻连接和通过网络的流水线数据移动来建立高数据速率。负载平衡的关键问题是基于(1)实现足够高的通信速率能力，以便网络链路被稀疏使用（即速率能力远远超过所需的数据速率）和(2)基于静电和势能的全局路由和负载平衡算法（即网络“活动电位”）。势能的分布式计算为每个本地节点提供了远离该节点的区域的缓慢变化的链路使用度量。具体研究完成了VLSI的设计和网络节点性能的电路仿真。此外，该研究开发了一个网络模拟器，以研究网络的稳态和瞬态行为，选择各种路由和负载平衡算法，以实现最大的VLSI面积/速度性能。

This research investigates the functional behavior and VLSI realization of a novel, scalable and intelligent wafer-level communications network (the Silicon Wafer Area Network or SWAN) supporting fine grained communications with predictable network traversal times. The network's "intelligence" is chosen to adaptively and dynamically establish virtual interconnections with the functionality of direct point-to-point interconnections for passage of individual messages through the network. The network is assumed to be a wafer-level function, allowing highly parallel data links between switches by exploiting the high density of IC wiring. The network organization is similar to a systolic processing array, using nearest neighbor connections and pipelined data movement through the network to establish high data rates. The critical issue of load balancing is based on (1) achieving sufficiently high communications rate capabilities so that network links are sparsely used (i.e. a rate capability well in excess of the required data rates) and (2) a global routing and load balancing algorithm based on electrostatic and potential energies (i.e. a network "activity potential"). The distributed computations of the potential energies provides each local node with a slowly varying measure of link usage in regions away from that node. The specific research completes VLSI design and circuit simulations of the performance of the network nodes. In addition, the research develops a network simulator to investigate the steady state and transient behavior of the network with various routing and load balancing algorithms selected to achieve the maximum VLSI area/speed performance.