NSF Young Investigator Award: High Performance Single Chip VLSI Processors

Farrens的研究是为了研究解耦体系结构的各种配置，并将这一概念扩展到并行处理领域。预计，随着几个解耦的处理器经由称为多指令流计算机(MISC)的体系结构队列进行通信，它将用作一种动态超标量处理器，从而提供显著的性能提升。MISC体系结构使用多个异步处理元件将程序分成可并行执行的流，并将无冲突的消息传递系统集成到处理器设计的最低层，以促进低延迟的MISC内通信。这种方法允许在最小代码扩展的情况下提高机器并行性，并为超标量和VLIW等单指令流多发布机器提供了一种替代方法。最优处理器配置和晶体管数量之间的关系也在研究中。目标是定义多处理器更改变得有利的设计点。

Farrens The research is to investigate various configurations of decoupled architectures and to extend the concept into the field of parallel processing. It is anticipated that, with several decoupled processors communicating via architectural queues called Multiple Instruction Stream Computer (MISC), it will function as a type of dynamic superscalar processor, providing significant performance gains. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conflict-free message passing system into the lowest level of the processor design to facilitate low latency intra-MISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as superscalars and VLIWs. The relationship between optimal processor configuration and transistor count is also being investigated. The goal is to define the design points at which a change to multiple processors becomes advantageous.