NSF Young Investigator Award: High Performance Single Chip VLSI Processors

NSF 青年研究员奖：高性能单芯片 VLSI 处理器

• 批准号: 9257259
• 负责人: Matthew Farrens
• 金额: $ 28.77万
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1992
• 资助国家: 美国
• 起止时间: 1992-10-01 至 1999-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9257259&HistoricalAwards=false
• 关键词: NSF; Young; Investigator; Award; Performance

Farrens The research is to investigate various configurations of decoupled architectures and to extend the concept into the field of parallel processing. It is anticipated that, with several decoupled processors communicating via architectural queues called Multiple Instruction Stream Computer (MISC), it will function as a type of dynamic superscalar processor, providing significant performance gains. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conflict-free message passing system into the lowest level of the processor design to facilitate low latency intra-MISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as superscalars and VLIWs. The relationship between optimal processor configuration and transistor count is also being investigated. The goal is to define the design points at which a change to multiple processors becomes advantageous.

法朗 本研究旨在探讨不同组态的解耦架构，并将此概念延伸至平行处理领域。 据预计，与几个解耦的处理器通过称为多指令流计算机（MISC）的架构队列进行通信，它将作为一种动态超标量处理器，提供显着的性能增益。 MISC架构使用多个异步处理元件将程序分离成可以并行执行的流，并将无冲突消息传递系统集成到处理器设计的最低级别中，以促进低延迟的MISC内通信。 这种方法允许以最小的代码扩展增加机器并行性，并为单指令流多发布机器（如超标量和VLIW）提供了一种替代方法。 最佳处理器配置和晶体管数量之间的关系也正在研究中。 目标是定义设计点，在这些设计点上，多处理器的变化变得有利。