NSF Young Investigator Award: High Performance Single Chip VLSI Processors

本研究旨在探讨解耦架构的各种配置，并将该概念扩展到并行处理领域。预计，通过称为多指令流计算机（MISC）的体系结构队列进行通信的几个解耦处理器将作为一种动态标量处理器，提供显着的性能提升。MISC架构使用多个异步处理元素将程序分离成可以并行执行的流，并将无冲突的消息传递系统集成到处理器设计的最底层，以促进低延迟的MISC内部通信。这种方法允许以最小的代码扩展来增加机器的并行性，并为单指令流多问题机器（如超标量和vliw）提供了另一种方法。最优处理器配置与晶体管数量之间的关系也在研究中。我们的目标是定义对多个处理器的更改变得有利的设计点。

Farrens The research is to investigate various configurations of decoupled architectures and to extend the concept into the field of parallel processing. It is anticipated that, with several decoupled processors communicating via architectural queues called Multiple Instruction Stream Computer (MISC), it will function as a type of dynamic superscalar processor, providing significant performance gains. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conflict-free message passing system into the lowest level of the processor design to facilitate low latency intra-MISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as superscalars and VLIWs. The relationship between optimal processor configuration and transistor count is also being investigated. The goal is to define the design points at which a change to multiple processors becomes advantageous.