Multi-Level Parallel Execution on Decoupled Systems

该项目正在研究基于分布式、去中心化（DD）计算方法的计算机体系结构。现在有必要重新审视传统的处理器架构概念，因为处理器周期时间和相对存储器访问时间之间的差距正在增加，在数十亿晶体管上分配高速同步时钟是困难的，并且随着处理器变得更加复杂，编译器分析变得更加智能，它们的接口必须得到改进。在本研究中，所使用的底层处理器模型在资源分配方面是分布式和分散式的，由多个独立可编程的处理元素组成，彼此连接的弹性和通过FIFO队列连接到内存。这种方法能够容忍内存延迟，克服时钟分布问题，并促进将编译器信息传输到硬件。该项目包括编译器技术的开发和一个分层模拟框架来证明这些主张。

This project is investigating computer architectures based on a distributed, decentralized (DD) approach to computing. It is now necessary to re-examine traditional concepts of processor architecture because the gap between processor cycle time and relative memory access time is increasing, distributing a high-speed synchronous clock to billions of transistors is difficult, and as processors become more complex and compiler analysis becomes more intelligent, their interface must be improved. In this research, the underlying processor model used is both distributed and decentralized in resource allocation, consisting of multiple independently programmable processing elements, elasticity connected to one another and to memory via FIFO queues. This approach is capable of tolerating memory latency, overcoming the clock distribution problem, and facilitating the transfer of compiler information to the hardware. This project includes the development of compiler technology and a hierarchical simulation framework to demonstrate these claims.