Multi-Level Parallel Execution on Decoupled Systems

解耦系统上的多级并行执行

• 批准号: 9812415
• 负责人: Matthew Farrens
• 金额: $ 55.12万
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1998
• 资助国家: 美国
• 起止时间: 1998-08-15 至 2003-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9812415&HistoricalAwards=false
• 关键词: Multi; Level; Parallel; Execution; Decoupled

This project is investigating computer architectures based on a distributed, decentralized (DD) approach to computing. It is now necessary to re-examine traditional concepts of processor architecture because the gap between processor cycle time and relative memory access time is increasing, distributing a high-speed synchronous clock to billions of transistors is difficult, and as processors become more complex and compiler analysis becomes more intelligent, their interface must be improved. In this research, the underlying processor model used is both distributed and decentralized in resource allocation, consisting of multiple independently programmable processing elements, elasticity connected to one another and to memory via FIFO queues. This approach is capable of tolerating memory latency, overcoming the clock distribution problem, and facilitating the transfer of compiler information to the hardware. This project includes the development of compiler technology and a hierarchical simulation framework to demonstrate these claims.

该项目正在研究基于分布式、分散(DD)计算方法的计算机体系结构。现在有必要重新审视处理器体系结构的传统概念，因为处理器周期时间和相对存储器访问时间之间的差距正在增加，为数十亿个晶体管分配高速同步时钟是困难的，随着处理器变得更加复杂，编译器分析变得更加智能，它们的接口必须得到改进。在本研究中，所使用的底层处理器模型在资源分配上既是分布式的，又是分散式的，由多个独立可编程的处理单元组成，通过FIFO队列彼此之间以及与内存的弹性连接。这种方法能够容忍内存延迟，克服时钟分布问题，并便于将编译器信息传输到硬件。该项目包括编译器技术的开发和一个层次化的模拟框架来演示这些主张。