Reducing I/O Pin Requirements for VLSI Processors

最近VLSI处理器速度的提高并没有与将处理器连接到片外存储器的I/O引脚数量的相应增加相匹配。处理器与片外存储器之间的带宽已成为制约超大规模集成电路系统性能的主要因素。已经开发了一种称为动态基寄存器缓存（DBRC）的压缩方案，它将地址引脚需求减少了两倍，而不会导致显著的性能损失或实现成本。这项工作将在几个方面进行扩展，以进一步减少处理器和内存之间的带宽需求。(1)通过利用后继信息来预测地址引用，有可能实现更高水平压缩的方案将被探索。(2)将研究类似的数据压缩方案。（初步测量表明，数据，如地址信息，是高度冗余的，所以一个简单的压缩方案是可能的。）(3)最后，对跟踪数据进行分析，建立地址流和数据参考流信息含量的严格上下限。精确的边界将表明可以压缩多少，以及可以改进多少方案。

Recent increases in VLSI processor speeds have not been matched by proportionate increase in the number of I/O pins that connect processors to off-chip memory. Bandwidth between processor and off-chip memory has become the primary constraint to VLSI system performance. A compression scheme know as Dynamic Base Register Caching (DBRC) has been developed that reduces address pin requirements by a factor of two without incurring a significant performance penalty or implementation cost. This work will be extended along several fronts to further reduce bandwidth requirements between processor and memory. (1) Schemes that have the potential to achieve even higher levels of compression by exploiting successor information to predict address references will be explored. (2) Analogous compression schemes for data will be investigated. (Preliminary measurements show that data, like address information, is highly redundant, so a simple compression scheme may be possible.) (3) Finally, trace data will be analyzed to establish tight upper and lower bounds on the information content of address and data reference streams. Accurate bounds will indicate how much compression is possible, as well as how much schemes can be improved.