The Design and Analysis of a High Performance Single Chip Processor

单芯片处理器的速度正在以惊人的速度增长，提供的原始处理能力正在迅速接近大型计算机。 不幸的是，外部存储器速度并没有表现出同样高的增长率，并且在高性能单芯片处理器中，外部存储器引用正在成为严重的性能瓶颈。 减少内存延迟对性能影响的一种方法是在处理器和外部内存之间合并架构 I/O 队列。 对在其处理器-内存接口中采用此类 I/O 队列（PIPE 处理器）的处理器的分析表明，这些队列能够而且确实提供了显着的性能改进。 然而，迄今为止所做的研究仅考察了 I/O 队列对科学程序的有效性。 本研究的目标是通过生成广泛的基准程序并分析它们在 PIPE 模拟器上的执行情况，更全面地评估 I/O 队列的整体有效性。 这些新的基准程序将通过为 PIPE 架构创建一个能够充分利用 I/O 队列的新优化编译器，或者通过修改为 ZS-1 编写的编译器的输出来生成，ZS-1 是一种商用产品，采用与 PIPE 处理器所使用的架构队列类似的架构队列。

Single-chip processor speeds are increaasing at a tremendous rate, providing raw processing power that is rapidly approaching that of mainframe computers. Unfortunately, external memory speeds are not exhibiting the same high rate of increase, and in high-performance single-chip processors external memory references are becoming a serious performance bottleneck. One way to reduce the impact of memory latency on performance is to incorporate architectural I/O queues between the processor and external memory. Analysis of a processor that employs such I/O queues (the PIPE processor) in its processor-memory interface indicates that these queues can and do provide significant performance improvements. However, the studies done so far have only looked at the effectiveness of I/O queues on scientific programs. The goal of this research is to more fully evaluate the overall effectiveness of I/O queues by generating a wide spectrum of benchmark programs and analyzing their execution on the PIPE simulator. These new benchmark programs will be produced by either creating a new optimizing compiler for the PIPE architecture that is capable of taking full advantage of the I/O queues, or by modifying the output of the compiler written for the ZS-1, a commercially available product that employs architectural queues similar to those used by the PIPE processor.