The Design and Analysis of a High Performance Single Chip Processor

一种高性能单片机的设计与分析

• 批准号: 9011535
• 负责人: Matthew Farrens
• 金额: $ 5.98万
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-06-15 至 1992-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9011535&HistoricalAwards=false
• 关键词: Design; Analysis; Performance; Single; Chip

Single-chip processor speeds are increaasing at a tremendous rate, providing raw processing power that is rapidly approaching that of mainframe computers. Unfortunately, external memory speeds are not exhibiting the same high rate of increase, and in high-performance single-chip processors external memory references are becoming a serious performance bottleneck. One way to reduce the impact of memory latency on performance is to incorporate architectural I/O queues between the processor and external memory. Analysis of a processor that employs such I/O queues (the PIPE processor) in its processor-memory interface indicates that these queues can and do provide significant performance improvements. However, the studies done so far have only looked at the effectiveness of I/O queues on scientific programs. The goal of this research is to more fully evaluate the overall effectiveness of I/O queues by generating a wide spectrum of benchmark programs and analyzing their execution on the PIPE simulator. These new benchmark programs will be produced by either creating a new optimizing compiler for the PIPE architecture that is capable of taking full advantage of the I/O queues, or by modifying the output of the compiler written for the ZS-1, a commercially available product that employs architectural queues similar to those used by the PIPE processor.

单芯片处理器的速度正在以惊人的速度增长， 提供的原始处理能力正在迅速接近 大型计算机。 不幸的是，外部存储器的速度不是 表现出同样高的增长率，并在高性能 单芯片处理器外部存储器引用正在成为 严重的性能瓶颈。 一种减少影响的方法是 内存延迟对性能的影响是将体系结构I/O 处理器和外部存储器之间的队列。 的分析 一个处理器采用这样的I/O队列（管道处理器），在其 处理器-内存接口指示这些队列可以并且确实 提供显著的性能改进。 然而，研究 到目前为止，我只研究了 科学计划。 这项研究的目的是更全面地 评估I/O队列的总体有效性，方法是生成一个广泛的 一系列基准测试程序，并分析它们在 管道模拟器。 这些新的基准程序将由 或者为PIPE架构创建新的优化编译器 能够充分利用I/O队列，或者通过 修改为ZS-1编写的编译器的输出， 使用体系结构队列的商用产品 类似于PIPE处理器所使用的那些。