Implementation of High Bandwidth Memory Systems

这个项目正在构建和测量实验存储系统，以匹配处理器的高数据速率和存储器部分的低随机访问数据速率。目标是在编译时检测内存引用流，并使用智能内存控制器在运行时预取这些流。内存控制器可以使用内存系统的特性，如页面模式、蚕食模式或Rambus，以最大限度地提高内存部分的数据速率。然后，它缓冲流，直到处理器请求数据。该项目包括编译器研究以及对内存控制器架构的研究。这与Cray超级计算机等机器上的向量化工作类似，但更通用，因为智能内存控制器可以设计为处理器速度、内存特性和程序特性的任何组合。

Wulf This project is building and measuring experimental memory systems that match the high data rates of processors with the low random access data rates of memory parts. The goal is to detect streams of memory references at compile time and use a smart memory controller to prefetch the streams at run time. The memory controller can use features of the memory system such as page mode, nibble mode, or Rambus to maximize the data rates of the memory parts. It then buffers the streams until the processor asks for the data. The project includes compiler research as well as research into the architecture of the memory controllers. This is similar to the vectorization efforts on such machines as the Cray supercomputers, but more general since a smart memory controller can be designed for any combination of processor speeds, memory features, and program characteristics.