Implementation of a High Performance Microprocessor

修订后的项目范围是对使用WM处理器的SYSTEM性能进行为期12个月的调查。特别地，调查是为了检查“WM系统的两个潜在瓶颈，即内存带宽和操作系统开销——特别是上下文切换”。因为超标量和超流水线处理器是内存“带宽饥渴者”（在WM处理器的情况下，每个处理器周期最多可以生成11个内存引用），所以有必要检查支持这种处理器所需的内存系统。指令缓存只能消除这些引用中的一个，而对于除一个之外的向量步进，数据缓存实际上可能会减少有效带宽。由于WM处理器的实现可能具有大量的内部状态（大于700字节），上下文切换的成本变得非常高，因为必须保存所有这些上下文（通常是在片外，因为片上的大部分空间都被寄存器、缓存等填充）。研究人员将探索几种设计方案来解决这些问题，以确定利用WM处理器构建高性能系统是否可行。

The revised project scope is for a 12-month investigation of the SYSTEM performance utilizing a WM processor. In particular, the investigation is to examine "two potential bottlenecks of WM systems, namely memory bandwidth and operating system overhead-- especially context switching". Because superscalar and superpipelined processors are memory "bandwidth hungry" (in the case of the WM processor up to 11 memory references can be generated per processor cycle)--there is a need to examine the memory system required to support such a processor. An instruction cache can only eliminate one of these references, while for vector strides other than one a data cache may actually REDUCE the effective bandwidth. Due to the large amount of internal state which an implementation of the WM processor might have (greater than 700 bytes)--the cost of a context switch becomes very high as all of this context must be saved (typically off-chip as most of the on-chip real-estate is filled with registers, cache,...). The investigators will explore several design alternatives to address each of these areas in order to determine if it is feasible to build a high-performance SYSTEM utilizing a WM processor.