Board Level Timing Verification

所提出的研究涉及分析验证板级电路中的组件接口的时序约束的满足。 提出了一种通过新的行为和验证模型对实际板级电路进行分析时序验证的方法，即VITCh（VLSI接口时序验证）。 一个层次模型的接口行为，允许任务被分解，以尽量减少整体的复杂性也提出了。 所提出的模型将允许板级电路的有效的时序分析，从而使大型和复杂的电路，现有的方法是无法验证的分析验证。 作为该项目的一部分，提出了一个CAD系统，实现VITCh提供一个实验验证的模型和方法的测试平台。 提议者试图通过将任务分解为几个可以并发执行的子任务来解决时序分析问题。 执行每个子任务，使得在电路行为枚举的过程期间验证时序约束，并且消除了构建和分析电路行为的复合表示的需要。 该研究计划包括测试VITCh的电路范围从几十到几百个组件，以建立作为电路大小的函数的算法的适用范围。

The proposed research deals with analytically verifying the satisfaction of timing constraints of component interfaces in board level circuits. A methodology, VITCh (VLSI Interface Timing Checker), that will allow the analytic timing verification of realistic board-level circuits through new models of behavior and verification is proposed. A hierarchial model of interface behavior that allows the task to be decomposed to minimize overall complexity is also proposed. The proposed model will allow efficient timing analysis of board-level circuits and thereby enable the analytical verification of large and complex circuits that existing approaches are unable to verify. A CAD system implementing VITCh to provide a testbed for experimentally validating the model and methodology is proposed as part of the project. The proposer attempts to solve the timing analysis problem by decomposing the task into several subtasks that can be executed concurrently. Each subtask is performed such that timing constraints are verified during the process of circuit behavior enumeration and eliminates the need to build and analyze composite representations of circuit behavior. The research plan includes testing VITCh on circuits ranging from tens to hundreds of components to establish the range of applicability of the algorithm as a function of circuit size.