Board Level Timing Verification

所提出的研究涉及分析验证板级电路中元件接口的时序约束的满足。提出了一种VLSI接口时序校验器(VLSI Interface Timing Checker，VLSI)方法，通过新的行为模型和验证模型对实际板级电路进行时序分析验证。提出了一种层次化的界面行为模型，该模型允许对任务进行分解以最大限度地降低总体复杂性。所提出的模型将允许对板级电路进行有效的时序分析，从而使现有方法无法验证的大型复杂电路的分析验证成为可能。作为项目的一部分，提出了一个实现VICH的CAD系统，为实验验证该模型和方法提供了测试平台。提出者试图通过将任务分解成几个可以并发执行的子任务来解决时序分析问题。每个子任务的执行使得在电路行为枚举过程中验证时序约束，并且消除了构建和分析电路行为的复合表示的需要。研究计划包括在数十到数百个元件的电路上测试VITCH，以确定该算法作为电路大小的函数的适用范围。

The proposed research deals with analytically verifying the satisfaction of timing constraints of component interfaces in board level circuits. A methodology, VITCh (VLSI Interface Timing Checker), that will allow the analytic timing verification of realistic board-level circuits through new models of behavior and verification is proposed. A hierarchial model of interface behavior that allows the task to be decomposed to minimize overall complexity is also proposed. The proposed model will allow efficient timing analysis of board-level circuits and thereby enable the analytical verification of large and complex circuits that existing approaches are unable to verify. A CAD system implementing VITCh to provide a testbed for experimentally validating the model and methodology is proposed as part of the project. The proposer attempts to solve the timing analysis problem by decomposing the task into several subtasks that can be executed concurrently. Each subtask is performed such that timing constraints are verified during the process of circuit behavior enumeration and eliminates the need to build and analyze composite representations of circuit behavior. The research plan includes testing VITCh on circuits ranging from tens to hundreds of components to establish the range of applicability of the algorithm as a function of circuit size.