Parallel Algorithms for Synthesis and Test

这项研究是在并行计算机上开发电路设计和测试算法。这些包括高效，异步，便携式并行算法，用于：(A)组合电路的合成；(B)用于组合电路和顺序电路的测试生成和故障模拟。算法正在使用一种环境来编写，这种环境使得在各种各样的MIMD机器上移植CAD应用程序成为可能。此外，它们的设计允许最大限度地重叠计算和通信。这些算法正在多个并行平台上进行测试。

This research is on developing circuit design and test algorithms that run on parallel computers. These include efficient, asynchronous, portable parallel algorithms for: (A) synthesis of combinational circuits; and (B) for test generation and fault simulation of combinational and sequential circuits. Algorithms are being written using an environment that makes it possible to port CAD applications across a wide range of MIMD machines. In addition they are designed to allow a maximum overlap of computation and communication. The algorithms are being tested on numerous parallel platforms.