Parallel Algorithms for VLSI Circuit Extraction on Multiprocessors

Banerjee博士的工作重点是VLSI CAD工具， 消息传递架构的类，例如超立方体。 在 这项研究，他将研究算法的工具， 执行从VLSI掩模布局中提取电路的任务。 技术方法是扁平化分层描述 转换成由矩形组成的掩码描述，并执行 在这个层面上的提取。 新的多处理器算法将 用于加速和精确的快速电路提取。 的 算法将在数据上并行使用区域查询 结构分布在并行处理器上。 是 预计这一程序将避免边界效应 当将VLSI布局区域划分为 地区

The focus of Dr. Banerjee's work is VLSI CAD tools which run on a class of message-passing architectures, such as hypercubes. In this research he will investigate algorithms for tools which perform the task of circuit extraction from VLSI mask layouts. The technical approach is to flatten the hierarchical description into a mask description consisting of rectangles, and perform the extraction at this level. The new multiprocessor algorithms will be used for speedup and accurate, fast-circuit extraction. The algorithms will use region queries in parallel on a data structure distributed over the parallel processor. It is anticipated that this procedure will avoid the boundary effect problems that may arise when splitting a VLSI layout area into regions.