Fault Tolerant Highly Parallel Signal Processing Architectures

VLSI中低成本、高密度、高速处理器和存储器的可用性，以及对信号处理高性能的日益增长的需求，导致了对高度并行的信号处理体系结构的大量建议。由于可靠性是一个关键要求，因此本研究针对这些并行体系结构中容错功能的设计所涉及的问题进行了研究。在这个项目中，具体、独特和有前景的容错方法是使用低成本的在线系统级错误检测和纠正技术，这些技术是根据在这些架构上执行的信号处理算法量身定做的。正在探索用于各种类型的信号处理算法的新型编码方案。从基于算法的检查的角度，研究了映射大问题对有限处理器网格连接结构的影响。目前正在研究有限精度算术对系统级编码的影响。基于算法的检查方案的故障复盖率和可靠性改进正在使用分析技术和功能模拟进行研究。最终，这项研究应该为基于算法的容错技术的设计确定一些基本原则。

The availability of low-cost, high-density, high-speed processors and memories in VLSI, together with the increasing demands for high-performance in signal processing, has resulted in numerous proposals for highly parallel signal processing architectures. Since reliability is a key requirement, this research addresses the issues involved in the design of fault tolerance features in these parallel architectures. The specific, unique and promising approach to fault tolerance in this project is the use of low- cost on-line system-level error detection and correction techniques, which are tailored to the signal processing algorithms being executed on these architectures. Novel encoding schemes for various classes of signal processing algorithms are being explored. The effects of mapping large problems on limited processor mesh-connected architectures are being investigated from the viewpoint of algorithm-based checking. The effects of finite precision arithmetic on system level encodings are being studied. The fault coverage and reliability improvements due to algorithm-based checking schemes are being investigated using analytical techniques as well as functional simulations. Eventually, the research should result in the identification of some basic principles for the design of algorithm-based fault tolerance techniques.