Fault Tolerant Highly Parallel Signal Processing Architectures

VLSI中低成本、高密度、高速处理器和存储器的可用性，以及对高性能信号处理的日益增长的需求，导致了许多关于高度并行信号处理架构的建议。由于可靠性是一个关键要求，本研究解决了这些并行体系结构中容错特性设计所涉及的问题。在这个项目中，特定的、独特的和有前途的容错方法是使用低成本的在线系统级错误检测和纠正技术，这些技术是针对在这些体系结构上执行的信号处理算法量身定制的。各种类型的信号处理算法的新编码方案正在被探索。从基于算法检查的角度研究了在有限处理器网格连接结构上映射大问题的影响。研究了有限精度算法对系统级编码的影响。基于算法的检查方案的故障覆盖率和可靠性改进正在使用分析技术和功能模拟进行研究。最后，研究结果应该是识别基于算法的容错技术设计的一些基本原则。

The availability of low-cost, high-density, high-speed processors and memories in VLSI, together with the increasing demands for high-performance in signal processing, has resulted in numerous proposals for highly parallel signal processing architectures. Since reliability is a key requirement, this research addresses the issues involved in the design of fault tolerance features in these parallel architectures. The specific, unique and promising approach to fault tolerance in this project is the use of low- cost on-line system-level error detection and correction techniques, which are tailored to the signal processing algorithms being executed on these architectures. Novel encoding schemes for various classes of signal processing algorithms are being explored. The effects of mapping large problems on limited processor mesh-connected architectures are being investigated from the viewpoint of algorithm-based checking. The effects of finite precision arithmetic on system level encodings are being studied. The fault coverage and reliability improvements due to algorithm-based checking schemes are being investigated using analytical techniques as well as functional simulations. Eventually, the research should result in the identification of some basic principles for the design of algorithm-based fault tolerance techniques.