Highly Continuous Sub-Half-Micron MOS Transistor Models for Low-Voltage, Low-Power VLSI Design

用于低压、低功耗 VLSI 设计的高度连续亚半微米 MOS 晶体管模型

• 批准号: 9322279
• 负责人: Bing Sheu
• 金额: $ 20.44万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1994
• 资助国家: 美国
• 起止时间: 1994-09-01 至 1997-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9322279&HistoricalAwards=false
• 关键词: Highly; Continuous; Sub; Half; Micron

9322279 Shen With rapid device miniaturization in microelectronic technologies and the recent drive for portable systems, very large-scale integration (VLSI) systems have been pushing toward low-voltage, low-power operation. In a mixed analog-digital VLSI circuit, many transistors will be biased around or below the threshold voltage to achieve the greatest performance. As the minimum device feature size decreases to below 0.4 micron, a reduction of the power supply voltage from 5 V to 3.3 V is necessary to avoid reliability problems caused by hot-carrier effects, thin-oxide breakdown, and metal electromigration. In the future, an even smaller power supply voltage in the 2 V range is anticipated. The fundamental objective of this research is directed towards the innovative development of complete MOS transistor models for deep-submicron digital and analog VLSI circuit designs including low-voltage, low-power applications. Three major research tasks are proposed: (1) comprehensive development of a sub-half-micron circuit-level MOS model based with major emphasis on physics-based parameter extraction; (2) derivation of continuous charge-based capacitance model for transient and small-signal analyses based on the same theoretical foundation for the drain current and conductance model; and (3) creative inclusion of analytical modeling based on continuous surface potential with special focus on efficiency. This research will establish the urgently needed sub-half-micron MOS transistor model for accurate analysis and simulation of logic and analog VLSI circuits, including low-voltage and low-power applications. It will provide the microelectronic industry and academic institutions with a new OS circuit-level model with high accuracy, good computational efficiency, and comprehensive completeness for computer-aided design applications. ***

随着微电子技术中器件的快速小型化和最近对便携式系统的推动，超大规模集成电路（VLSI）系统一直在向低电压、低功耗工作方向发展。在混合模拟-数字VLSI电路中，许多晶体管将被偏置在阈值电压附近或低于阈值电压，以实现最佳性能。 由于最小器件特征尺寸减小到0.4微米以下，因此有必要将电源电压从5 V降低到3.3 V，以避免热载流子效应、薄氧化物击穿和金属电迁移引起的可靠性问题。 在未来，预计在2 V范围内的更小的电源电压。 本研究的基本目标是针对深亚微米数字和模拟VLSI电路设计，包括低电压，低功耗应用的完整的MOS晶体管模型的创新发展。 提出了三个主要的研究任务：（1）全面发展亚半微米电路级MOS模型，重点是基于物理的参数提取：（2）在漏电流和电导模型的理论基础上，推导出用于瞬态和小信号分析的基于连续电荷的电容模型;以及（3）创造性地包含基于连续表面势的分析建模，特别关注效率。 这项研究将建立迫切需要的亚半微米MOS晶体管模型，用于精确分析和模拟逻辑和模拟VLSI电路，包括低电压和低功耗应用。 它将为微电子工业和学术机构提供一个新的OS电路级模型，具有高精度，良好的计算效率和全面的完整性，用于计算机辅助设计应用。 ***