Highly Continuous Sub-Half-Micron MOS Transistor Models for Low-Voltage, Low-Power VLSI Design

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9322279 Shen With rapid device miniaturization in microelectronic technologies and the recent drive for portable systems, very large-scale integration (VLSI) systems have been pushing toward low-voltage, low-power operation. In a mixed analog-digital VLSI circuit, many transistors will be biased around or below the threshold voltage to achieve the greatest performance. As the minimum device feature size decreases to below 0.4 micron, a reduction of the power supply voltage from 5 V to 3.3 V is necessary to avoid reliability problems caused by hot-carrier effects, thin-oxide breakdown, and metal electromigration. In the future, an even smaller power supply voltage in the 2 V range is anticipated. The fundamental objective of this research is directed towards the innovative development of complete MOS transistor models for deep-submicron digital and analog VLSI circuit designs including low-voltage, low-power applications. Three major research tasks are proposed: (1) comprehensive development of a sub-half-micron circuit-level MOS model based with major emphasis on physics-based parameter extraction; (2) derivation of continuous charge-based capacitance model for transient and small-signal analyses based on the same theoretical foundation for the drain current and conductance model; and (3) creative inclusion of analytical modeling based on continuous surface potential with special focus on efficiency. This research will establish the urgently needed sub-half-micron MOS transistor model for accurate analysis and simulation of logic and analog VLSI circuits, including low-voltage and low-power applications. It will provide the microelectronic industry and academic institutions with a new OS circuit-level model with high accuracy, good computational efficiency, and comprehensive completeness for computer-aided design applications. ***