RESEARCH INITIATION AWARD: Kinetics and Structure of Vertical Isolation for VLSI Circuits Formed by Low Temperature Oxidation of Silicon

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9410399 Alford This investigation will study the low temperature oxidation of Si in contact with Cu-Silicide. The kinetics of the phenomena, characterization of the oxide layer, and use of the orientation dependence on growth rate to form vertical isolation oxides in integrated circuits shall be investigated. At room temperature Cu-silicide forms an oxide layer between the Si and silicide interface when exposed to air. The oxide layer grows to a thickness of several microns in a period of weeks. The growth kinetics, will be characterized to obtain activation energy, substrate orientation, identity of moving species (use of implanted makers), and influence of dopants and impurities. The integrity of the growth oxide will be quantified by electrical measurements (MOS capacitor structures, I-V, C-V), ion-beam analysis (composition, density, and impurities), and transmission electron microscopy (microstructure). ***