NSF Young Investigator: Design Automation for Embedded Systems

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High fabrication costs coupled with decreasing time-to-market for products require an increase of the programmable component of integrated circuits. Core processors embedded in a gate array provide programmability. This changes circuit design from just gates in an array, to a combination of instructions running on a core processor coupled with a gate array. Gates, as basic units of computation on silicon, are well understood. This research is focused on understanding embedded instructions as basic units of computation on silicon. Initial work is on finding methodologies for synthesizing embedded software. Problems being examined are: worst case timing analysis; power modeling and analysis; and high- quality retargetable code synthesis. Approaches include: developing timing models capable of handling features such as caches and pipelines, and determining worst-case paths; analyzing system power consumption; and formal architectural specification of specialized architectures, as well as code-generation algorithms that can take advantage of special architectures.