XPS: FULL: Hardware Software Abstractions: Addressing Specification and Verification Gaps in Accelerator-Oriented Parallelism

鉴于半导体技术扩展的减速，将处理器性能扩展保持在可接受的功率限制已变得越来越具有挑战性。作为回应，微处理器越来越多地使用具有异类并行性的复杂体系结构和称为加速器的专用计算单元。加速器通过避免指令可编程性开销，以更低的功率/能量提供高计算性能。然而，关键的挑战是，与传统的微处理器CPU不同，加速器没有耐用的、可移植的指令集体系结构(ISA)，而是通过驱动程序或库API进行编程。这些增加了将面向加速器的程序移植到具有类似功能但不同实现的其他平台的努力。增加的努力对软件成本产生了严重的后果。此外，加速器没有正式、持久的ISA，这一事实导致了验证复杂性的增加，而此时它已经是未来计算平台设计的限制因素。这项工作的学术价值在于，该研究正在开发指令级抽象(ILA)，将ISA概念扩展到加速器，以应对这些编程和验证挑战。ILAS提供加速器将在每次调用上执行的可见状态更新的正式和高级摘要。S项目的更广泛的意义和重要性是该工作？S能够影响未来基于加速器的计算平台的行业设计，从而帮助支撑美国计算行业。ILA有两个组件：指定状态更新和指定内存一致性模型，即相对于其他并行计算元素允许的状态更新顺序。该研究开发的ILA方法是(I)跨加速器统一的，(Ii)与指令可编程处理器的ISA对称的，以及(Iii)跨计算(状态改变)和内存(数据/存储状态更新)抽象的统一的。为了显示ILA的价值，研究开发了：(I)丰富加速器集的ILA规范机制，(Ii)自动生成这些ILA的综合技术和工具，(Iii)对照实现检查这些抽象的验证技术和工具，以及(Iv)由ILA支持的其他工具，包括全系统体系结构模拟。通过这些努力，这项工作解决了面向加速器的系统设计和部署中的基本软件可移植性和验证差距。

Given slowdowns in semiconductor technology scaling, it has become increasingly challenging to maintain processor performance scaling at acceptable power constraints. In response, microprocessors increasingly use complex architectures with heterogeneous parallelism and specialized compute units known as accelerators. Accelerators provide high compute performance at reduced power/energy by avoiding the overhead of instruction-programmability. The key challenge, however, is that unlike traditional microprocessor CPUs, accelerators have no durable, portable instruction set architecture (ISA), and instead are programmed via drivers or library APIs. These increase the effort of porting accelerator-oriented programs to other platforms with similar functionality but different implementations. The increased effort has serious consequences for software cost. Furthermore, the fact that accelerators have no formal, durable ISA causes increased verification complexity at a time when it is already the limiting factor in the design of future computing platforms. The intellectual merits of this work are that the research is developing Instruction-Level Abstractions (ILAs) that extend the ISA concept to accelerators in order to address these programming and verification challenges. ILAs offer a formal and high-level summary of the visible state updates that an accelerator will perform on each invocation. The project?s broader significance and importance are the work?s ability to impact industry designs of future accelerator-based computing platforms and thereby help sustain the US computing industry.There are two components to an ILA: specifying the state updates, and specifying the Memory Consistency Model, i.e., the permitted ordering of state updates relative to other parallel compute elements. The research develops ILA methodologies that are (i) uniform across accelerators, (ii) symmetric with the ISA of instruction-programmable processors and (iii) unified across both computation (state change) and memory (data/storage state update) abstractions. To show the value of ILAs, the research develops: (i) ILA specification mechanisms for a rich set of accelerators, (ii) synthesis techniques and tools for generating these ILAs automatically, (iii) verification techniques and tools that check these abstractions against implementations and (iv) further tools enabled by ILAs including full-system architectural simulation. Through these efforts, this work addresses fundamental software portability and verification gaps in the design and deployment of accelerator-oriented systems.