SBIR Phase II: A Demultiplexer for Processing Ultra-High- Speed Data from Superconducting Circuits

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9501322 Kaplan This Small Business Innovation Research (SBIR) Phase II project will develop a superconductive demultiplexer (demux) designed to slow the data stream from superconductive circuits and to serve as the interface with room-temperature circuits. Phase I successfully demonstrated a modular architecture that uses non-destructive read-out (NDRO) cells as well as a two-stage demux equipped with two NDRO cells. Phase II is expected to demonstrate a transient digitizer chip containing a flash analog-to-digital converter (ADC) and a number of demux units, which divert high-speed digital data into an appropriate number of lower-speed channels. Each demux output channel can be clocked at a rate low enough for room-temperature hardware to acquire and reconstruct the signal. This technology will exploit the inherent advantage of superconductive ADCs whose very large bandwidth is unmatched by semiconductor technology. A superconductive demux will permit superconductive chips to be incorporated in semiconducting system designs.