A Demultiplexer for Processing Ultra High Speed Data from Superconducting Circuits

事实证明，9360144卡普兰超导电路在处理超高速数据流方面是有效的。例如，HYPRES已经展示了一个8位模数转换器(ADC)，在4 GHz时有4.4个有效位，在7 GHz时有2个有效位。我们预计在10 GHz下ADC的性能为6个有效比特。然而，超导电路以如此高的数据速率工作的能力使得与室温电路的通信变得困难。我们在这项提案中解决了这个问题。我们建议设计、制造和测试一个多路分解器电路，以将高速数据转移到多个低速通道。每个通道的时钟将以传统电路足够低的速率计时。该多路分解器将与我们的ADC兼容，并且将足够通用，以用于数据速率对于传统电路来说太高的其他应用。在第一阶段，将使用1：4多路分解器演示原理证明。该设计将是模块化的，因此扩展到具有更大解复用器比率的电路是直接的。在第二阶段，多路分解器的操作将作为高速单片ADC芯片的一部分进行演示。***

9360144 Kaplan Superconductive circuits are proving effective in processing very high speed data streams. For example, HYPRES has demonstrated an 8-bit analog-to-digital converter (ADC) with 4.4 effective bits at 4 GHz, and 2 effective bits at 7 GHz. We project an ADC performance of 6 effective bit at 10 GHz. However, the ability of superconductive circuits to work at such high data rates renders it difficult to communicate with room-temperature circuitry. We address this problem in this proposal. We propose to design, fabricate and test a demultiplexer circuit to divert high-speed data into several lower-speed channels. Each channel will be clocked at a rate low enough for conventional circuits. The demultiplexer will be compatible with our ADC, and will be general enough to be used in other applications where the data rate is too high for conventional circuits. During Phase I, proof of principle will be demonstrated with a 1:4 demultiplexer. The design will be modular so that extension to a circuit with a larger demultiplexer ratio is be straightforward. In Phase II, the operation of the demultiplexer will be demonstrated as part of a high-speed monolithic ADC chip. ***