A Demultiplexer for Processing Ultra High Speed Data from Superconducting Circuits

超导电路在处理高速数据流方面被证明是有效的。例如，HYPRES已经展示了一个8位模数转换器（ADC），在4 GHz时具有4.4位有效位，在7 GHz时具有2位有效位。我们预计在10ghz时ADC性能为6有效位。然而，超导电路在如此高的数据速率下工作的能力使得它很难与室温电路通信。我们在本建议中讨论这个问题。我们建议设计，制造和测试一个解复用电路，将高速数据分流到几个低速通道。对于传统电路来说，每个通道的时钟速率都足够低。解复用器将与我们的ADC兼容，并且将足够通用，用于数据速率对于传统电路来说太高的其他应用。在第一阶段，原理证明将用1:4解复用器进行演示。该设计将是模块化的，因此扩展到具有更大解复用比的电路是直接的。在第二阶段，解复用器的操作将作为高速单片ADC芯片的一部分进行演示。＊＊＊

9360144 Kaplan Superconductive circuits are proving effective in processing very high speed data streams. For example, HYPRES has demonstrated an 8-bit analog-to-digital converter (ADC) with 4.4 effective bits at 4 GHz, and 2 effective bits at 7 GHz. We project an ADC performance of 6 effective bit at 10 GHz. However, the ability of superconductive circuits to work at such high data rates renders it difficult to communicate with room-temperature circuitry. We address this problem in this proposal. We propose to design, fabricate and test a demultiplexer circuit to divert high-speed data into several lower-speed channels. Each channel will be clocked at a rate low enough for conventional circuits. The demultiplexer will be compatible with our ADC, and will be general enough to be used in other applications where the data rate is too high for conventional circuits. During Phase I, proof of principle will be demonstrated with a 1:4 demultiplexer. The design will be modular so that extension to a circuit with a larger demultiplexer ratio is be straightforward. In Phase II, the operation of the demultiplexer will be demonstrated as part of a high-speed monolithic ADC chip. ***