Concurrent Optimization of Cell Libraries and Fabrication Processes

本研究提出了开发电路单元库和制造过程同时优化的技术。所提出的方法的一个关键优点是，它允许电路设计师和制造工艺工程师朝着最大产量的共同目标努力，这将反过来降低产品成本。第二个优点是，通过并行工程，这种方法可以显著减少产品开发时间。为在工业环境中验证所建议的技术作出了规定。该提案的研究部分也被一个广泛的教育计划所补充，该计划将并行设计研究整合到本科课程中。

This research proposes to develop techniques for concurrent optimization of both the circuit cell libraries and the fabrication process. A key advantage of the proposed approach is that it allows both the circuit designer and fabrication process engineer to work towards the common goal of maximizing yield, which will in turn reduce product cost. A second advantage is that through concurrent engineering, this approach can significantly reduce product development time. Provisions have been made for validating proposed techniques in an industrial setting. The research component of this proposal is also complemented by an extensive education plan for integrating studies in concurrent design into the undergraduate curriculum.